Datasheet
Table Of Contents
- Features
- Description
- Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN
- Pin Designation – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN
- Functional Block Diagram – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC, MSP430F5522IRGC MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
- Pin Designation – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC, MSP430F5522IRGC
- Functional Block Diagram – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
- Pin Designation – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
- Functional Block Diagram – MSP430F5514IRGC, MSP430F5513IRGC, MSP430F5514IZQE, MSP430F5513IZQE
- Pin Designation – MSP430F5514IRGC, MSP430F5513IRGC
- Pin Designation – MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE, MSP430F5514IZQE, MSP430F5513IZQE
- Pin Designation – MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
- Short-Form Description
- CPU
- Operating Modes
- Interrupt Vector Addresses
- Memory Organization
- Bootstrap Loader (BSL)
- JTAG Operation
- Flash Memory (Link to User's Guide)
- RAM Memory (Link to User's Guide)
- Peripherals
- Digital I/O (Link to User's Guide)
- Port Mapping Controller (Link to User's Guide)
- Oscillator and System Clock (Link to User's Guide)
- Power Management Module (PMM) (Link to User's Guide)
- Hardware Multiplier (Link to User's Guide)
- Real-Time Clock (RTC_A) (Link to User's Guide)
- Watchdog Timer (WDT_A) (Link to User's Guide)
- System Module (SYS) (Link to User's Guide)
- DMA Controller (Link to User's Guide)
- Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
- TA0 (Link to User's Guide)
- TA1 (Link to User's Guide)
- TA2 (Link to User's Guide)
- TB0 (Link to User's Guide)
- Comparator_B (Link to User's Guide)
- ADC12_A (Link to User's Guide)
- CRC16 (Link to User's Guide)
- REF Voltage Reference (Link to User's Guide)
- USB Universal Serial Bus (Link to User's Guide)
- Embedded Emulation Module (EEM) (Link to User's Guide)
- Peripheral File Map
- Absolute Maximum Ratings
- Thermal Packaging Characteristics
- Recommended Operating Conditions
- Electrical Characteristics
- Active Mode Supply Current Into VCC Excluding External Current
- Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- Schmitt-Trigger Inputs – General Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
- Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
- Leakage Current – General Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
- Outputs – General Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
- Outputs – General Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
- Output Frequency – General Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
- Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- Crystal Oscillator, XT1, Low-Frequency Mode
- Crystal Oscillator, XT2
- Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- Internal Reference, Low-Frequency Oscillator (REFO)
- DCO Frequency
- PMM, Brown-Out Reset (BOR)
- PMM, Core Voltage
- PMM, SVS High Side
- PMM, SVM High Side
- PMM, SVS Low Side
- PMM, SVM Low Side
- Wake-Up From Low-Power Modes and Reset
- Timer_A
- Timer_B
- USCI (UART Mode) Recommended Operating Conditions
- USCI (UART Mode)
- USCI (SPI Master Mode) Recommended Operating Conditions
- USCI (SPI Master Mode)
- USCI (SPI Slave Mode)
- USCI (I2C Mode)
- 12-Bit ADC, Power Supply and Input Range Conditions
- 12-Bit ADC, Timing Parameters
- 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
- 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
- 12-Bit ADC, Temperature Sensor and Built-In VMID
- REF, External Reference
- REF, Built-In Reference
- Comparator_B
- Ports PU.0 and PU.1
- USB Output Ports DP and DM
- USB Input Ports DP and DM
- USB-PWR (USB Power System)
- USB-PLL (USB Phase Locked Loop)
- Flash Memory
- JTAG and Spy-Bi-Wire Interface
- Input/Output Schematics
- Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
- Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
- Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
- Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
- Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
- Port P5, P5.2, Input/Output With Schmitt Trigger
- Port P5, P5.3, Input/Output With Schmitt Trigger
- Port P5, P5.6 to P5.7, Input/Output With Schmitt Trigger
- Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
- Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger
- Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
- Port P8, P8.0 to P8.2, Input/Output With Schmitt Trigger
- Port PU.0/DP, PU.1/DM, PUR USB Ports
- Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
- Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- Device Descriptors (TLV)
- Revision History
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526
MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
www.ti.com
SLAS590L –MARCH 2009–REVISED MAY 2013
Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1) (2)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
f
OSC
= 4 MHz, XT2OFF = 0, XT2BYPASS = 0,
200
XT2DRIVEx = 0, T
A
= 25°C
f
OSC
= 12 MHz, XT2OFF = 0, XT2BYPASS = 0,
260
XT2DRIVEx = 1, T
A
= 25°C
XT2 oscillator crystal
I
DVCC.XT2
3.0 V µA
current consumption
f
OSC
= 20 MHz, XT2OFF = 0, XT2BYPASS = 0,
325
XT2DRIVEx = 2, T
A
= 25°C
f
OSC
= 32 MHz, XT2OFF = 0, XT2BYPASS = 0,
450
XT2DRIVEx = 3, T
A
= 25°C
XT2 oscillator crystal
f
XT2,HF0
XT2DRIVEx = 0, XT2BYPASS = 0
(3)
4 8 MHz
frequency, mode 0
XT2 oscillator crystal
f
XT2,HF1
XT2DRIVEx = 1, XT2BYPASS = 0
(3)
8 16 MHz
frequency, mode 1
XT2 oscillator crystal
f
XT2,HF2
XT2DRIVEx = 2, XT2BYPASS = 0
(3)
16 24 MHz
frequency, mode 2
XT2 oscillator crystal
f
XT2,HF3
XT2DRIVEx = 3, XT2BYPASS = 0
(3)
24 32 MHz
frequency, mode 3
XT2 oscillator logic-level
f
XT2,HF,SW
square-wave input XT2BYPASS = 1
(4) (3)
0.7 32 MHz
frequency, bypass mode
XT2DRIVEx = 0, XT2BYPASS = 0,
450
f
XT2,HF0
= 6 MHz, C
L,eff
= 15 pF
XT2DRIVEx = 1, XT2BYPASS = 0,
320
f
XT2,HF1
= 12 MHz, C
L,eff
= 15 pF
Oscillation allowance for
OA
HF
Ω
HF crystals
(5)
XT2DRIVEx = 2, XT2BYPASS = 0,
200
f
XT2,HF2
= 20 MHz, C
L,eff
= 15 pF
XT2DRIVEx = 3, XT2BYPASS = 0,
200
f
XT2,HF3
= 32 MHz, C
L,eff
= 15 pF
f
OSC
= 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0,
0.5
T
A
= 25°C, C
L,eff
= 15 pF
t
START,HF
Startup time 3.0 V ms
f
OSC
= 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 2,
0.3
T
A
= 25°C, C
L,eff
= 15 pF
Integrated effective load
C
L,eff
capacitance, HF 1 pF
mode
(6)(1)
Duty cycle Measured at ACLK, f
XT2,HF2
= 20 MHz 40 50 60 %
Oscillator fault
f
Fault,HF
XT2BYPASS = 1
(8)
30 300 kHz
frequency
(7)
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance
of up to 18 pF can be supported.
(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513