Datasheet

MSP430F5510, MSP430F5509, MSP430F5508, MSP430F5507
MSP430F5506, MSP430F5505, MSP430F5504, MSP430F5503
MSP430F5502, MSP430F5501, MSP430F5500
www.ti.com SLAS645I –JULY 2009–REVISED NOVEMBER 2013
10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
1.4 V ≤ (V
eREF+
– V
eREF–
)min ≤ 1.6 V ±1.0
Integral
E
I
2.2 V, 3 V LSB
linearity error
1.6 V < (V
eREF+
– V
eREF–
)min ≤ V
AVCC
±1.0
Differential (V
eREF+
– V
eREF–
)min ≤ (V
eREF+
– V
eREF–
),
E
D
2.2 V, 3 V ±1.0 LSB
linearity error C
VREF+
= 20 pF
(V
eREF+
– V
eREF–
)min ≤ (V
eREF+
– V
eREF–
),
E
O
Offset error 2.2 V, 3 V ±1.0 LSB
Internal impedance of source R
S
< 100 Ω, C
VREF+
= 20 pF
(V
eREF+
– V
eREF–
)min ≤ (V
eREF+
– V
eREF–
),
E
G
Gain error 2.2 V, 3 V ±1.0 LSB
C
VREF+
= 20 pF
Total unadjusted (V
eREF+
– V
REF–
/V
eREF–
)min ≤ (V
eREF+
– V
REF–
/V
eREF–
),
E
T
2.2 V, 3 V ±1.0 ±2.0 LSB
error C
VREF+
= 20 pF
REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Positive external reference
V
eREF+
V
eREF+
> V
eREF–
(2)
1.4 AV
CC
V
voltage input
Negative external
V
eREF–
V
eREF+
> V
eREF–
(3)
0 1.2 V
reference voltage input
(V
eREF+
– Differential external
V
eREF+
> V
eREF–
(4)
1.4 AV
CC
V
V
eREF–
) reference voltage input
1.4 V ≤ V
eREF+
≤ V
AVCC
, V
eREF–
= 0 V,
f
ADC10CLK
= 5 MHz, ADC10SHTx = 0x0001, 2.2 V, 3 V ±8.5 ±26 µA
Conversion rate 200 ksps
I
VeREF+
Static input current
I
VeREF–
1.4 V ≤ V
eREF+
≤ V
AVCC
, V
eREF–
= 0 V,
f
ADC10CLK
= 5 MHZ, ADC10SHTX = 0x1000, 2.2 V, 3 V ±1 µA
Conversion rate 20 ksps
Capacitance at VeREF+
C
VeREF+/-
(5)
10 µF
or VeREF- terminal
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C
I
, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
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