Datasheet

MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
SLAS612D –AUGUST 2009–REVISED AUGUST 2013 www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage V
CC
applied at supply pins DVCC/AVCC to supply pins DVSS/AVSS –0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE)
(2)
–0.3 V to V
CC
+ 0.3 V
Diode current at any device pin ±2 mA
Storage temperature range
(3)
, T
stg
–55°C to 150°C
Maximum operating junction temperature, T
J
95°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics
VALUE UNIT
LQFP (PZ) 50.1
Low-K board (JESD51-3)
LQFP (PN) 57.9
θ
JA
Junction-to-ambient thermal resistance, still air °C/W
LQFP (PZ) 40.8
High-K board (JESD51-7)
LQFP (PN) 37.9
LQFP (PZ) 8.9
θ
JC
Junction-to-case thermal resistance °C/W
LQFP (PN) 10.3
Recommended Operating Conditions
Typical values are specified at V
CC
= 3.3 V and T
A
= 25°C (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage during program execution and flash programming
V
CC
2.2 3.6 V
(V
CC
= DV
CC1/2/3/4
= AV
CC
)
(1)(2)
V
SS
Supply voltage (V
SS
= DV
SS1/2/3/4
= DV
SS
= AV
SS
) 0 V
T
A
Operating free-air temperature I version -40 85 °C
T
J
Operating junction temperature I version -40 85 °C
CVCORE Recommended capacitor at VCORE 470 nF
CDVCC/
Capacitor ratio of DVCC to VCORE 10
CVCORE
PMMCOREVx = 2,
f
SYSTEM
Processor frequency (maximum MCLK frequency)
(3) (4)
(see Figure 2) 0 18 MHz
2.2 V ≤ V
CC
≤ 3.6 V
(1) It is recommended to power AV
CC
and DV
CC
from the same source. A maximum difference of 0.3 V between AV
CC
and DV
CC
can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
(3) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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