Datasheet

P5.3/XT2OUT
P5SEL.3
1
0
P5DIR.3
P5IN.3
EN
Module X IN
1
0
Module X OUT
P5OUT.3
1
0
DV
SS
DV
CC
P5REN.3
Pad Logic
1
P5DS.3
0: Low drive
1: High drive
D
Bus
Keeper
To XT2
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A
MSP430F5419A, MSP430F5418A
SLAS655D –JANUARY 2010–REVISED AUGUST 2013 www.ti.com
Port P5, P5.3, Input/Output With Schmitt Trigger
Table 49. Port P5 (P5.2) Pin Functions
CONTROL BITS/SIGNALS
(1)
PIN NAME (P5.x) x FUNCTION
P5DIR.x P5SEL.2 P5SEL.3 XT2BYPASS
P5.2/XT2IN 2 P5.2 (I/O) I: 0; O: 1 0 X X
XT2IN crystal mode
(2)
X 1 X 0
XT2IN bypass mode
(2)
X 1 X 1
P5.3/XT2OUT 3 P5.3 (I/O) I: 0; O: 1 0 X X
XT2OUT crystal mode
(3)
X 1 X 0
P5.3 (I/O)
(3)
X 1 X 1
(1) X = Don't care
(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
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