Datasheet

SDA
SCL
t
HD,DAT
t
SU,DAT
t
HD,STA
t
HIGH
t
LOW
t
BUF
t
HD,STA
t
SU,STA
t
SP
t
SU,STO
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A
MSP430F5419A, MSP430F5418A
www.ti.com SLAS655D –JANUARY 2010–REVISED AUGUST 2013
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK,
f
USCI
USCI input clock frequency External: UCLK, f
SYSTEM
MHz
Duty cycle = 50% ± 10%
f
SCL
SCL clock frequency 2.2 V, 3 V 0 400 kHz
f
SCL
≤ 100 kHz 4.0
t
HD,STA
Hold time (repeated) START 2.2 V, 3 V µs
f
SCL
> 100 kHz 0.6
f
SCL
≤ 100 kHz 4.7
t
SU,STA
Setup time for a repeated START 2.2 V, 3 V µs
f
SCL
> 100 kHz 0.6
t
HD,DAT
Data hold time 2.2 V, 3 V 0 ns
t
SU,DAT
Data setup time 2.2 V, 3 V 250 ns
f
SCL
≤ 100 kHz 4.0
t
SU,STO
Setup time for STOP 2.2 V, 3 V µs
f
SCL
> 100 kHz 0.6
2.2 V 50 600
Pulse duration of spikes suppressed by input
t
SP
ns
filter
3 V 50 600
Figure 16. I2C Mode Timing
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