Datasheet

MSP430F532x
SLAS678D –AUGUST 2010–REVISED FEBRUARY 2013 www.ti.com
USCI (UART Mode) Recommended Operating Conditions
PARAMETER CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK,
f
USCI
USCI input clock frequency External: UCLK, f
SYSTEM
MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
f
BITCLK
1 MHz
(equals baud rate in MBaud)
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
2.2 V 50 600
t
τ
UART receive deglitch time
(1)
ns
3 V 50 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK,
f
USCI
USCI input clock frequency f
SYSTEM
MHz
Duty cycle = 50% ± 10%
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1)
, Figure 11 and Figure 12)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
SMCLK, ACLK
f
USCI
USCI input clock frequency f
SYSTEM
MHz
Duty cycle = 50% ± 10%
1.8 V 55
PMMCOREV = 0 ns
3 V 38
t
SU,MI
SOMI input data setup time
2.4 V 30
PMMCOREV = 3 ns
3 V 25
1.8 V 0
PMMCOREV = 0 ns
3 V 0
t
HD,MI
SOMI input data hold time
2.4 V 0
PMMCOREV = 3 ns
3 V 0
1.8 V 20
UCLK edge to SIMO valid,
ns
C
L
= 20 pF, PMMCOREV = 0
3 V 18
t
VALID,MO
SIMO output data valid time
(2)
2.4 V 16
UCLK edge to SIMO valid,
ns
C
L
= 20 pF, PMMCOREV = 3
3 V 15
1.8 V -10
C
L
= 20 pF, PMMCOREV = 0 ns
3 V -8
t
HD,MO
SIMO output data hold time
(3)
2.4 V -10
C
L
= 20 pF, PMMCOREV = 3 ns
3 V -8
(1) f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
≥ max(t
VALID,MO(USCI)
+ t
SU,SI(Slave)
, t
SU,MI(USCI)
+ t
VALID,SO(Slave)
).
For the slave's parameters t
SU,SI(Slave)
and t
VALID,SO(Slave)
see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 11 and Figure 12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 11 and Figure 12.
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