Datasheet

MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU goes
into LPM4 immediately after power-up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out−of−Range (see Note 4)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 14
Timer_B3 TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13
Timer_B3
TBCCR1 to TBCCR2 CCIFGs
TBIFG (see Notes 1 and 2)
Maskable 0FFF8h 12
Comparator_A CAIFG Maskable 0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
USCI_A0/B0 Receive UCA0RXIFG, UCB0RXIFG
(see Note 1 and 5)
Maskable 0FFF2h 9
USCI_A0/B0 Transmit UCA0TXIFG, UCB0TXIFG
(see Note 1 and 6)
Maskable 0FFF0h 8
SD16_A SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable 0FFEEh 7
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6
Timer_A3
TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2)
Maskable 0FFEAh 5
I/O Port P1
(Eight Flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
Maskable 0FFE8h 4
USCI_A1/B1 Receive UCA1RXIFG, UCB1RXIFG
(see Notes 1 and 2)
Maskable 0FFE6h 3
USCI_A1/B1 Transmit UCA1TXIFG, UCB1TXIFG
(see Notes 1 and 2)
Maskable 0FFE4h 2
I/O Port P2
(Eight Flags)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG in register UCB0STAT.
6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
7. In SPI mode: UCB1RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG in register UCB1STAT.
8. In UART/SPI mode: UCB1TXIFG. In I2C mode: UCB1RXIFG, UCB1TXIFG.