Datasheet

MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
51
POST OFFICE BOX 655303  DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (SPI slave mode) (see Note 1, Figure 23, and Figure 24)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
t
STE,LEAD
STE lead time
STE low to clock
2.2 V/3 V 50 ns
t
STE,LAG
STE lag time
Last clock to STE high
2.2 V/3 V 10 ns
t
STE,ACC
STE access time
STE low to SOMI data out
2.2 V/3 V 50 ns
t
STE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V/3 V 50 ns
t
S
I
M
O
i
n
p
u
t
d
a
t
a
s
e
t
u
p
t
i
m
e
2.2 V 20 ns
t
SU,SI
SIMO input data setup time
3V 15 ns
t
S
I
M
O
i
n
p
u
t
d
a
t
a
h
o
l
d
t
i
m
e
2.2 V 10 ns
t
HD,SI
SIMO input data hold time
3V 10 ns
t
S
O
M
I
o
u
t
p
u
t
d
a
t
a
v
a
l
i
d
t
i
m
e
(
N
o
t
e
2
)
UCLK ed
g
etoSOMIvalid,
2.2 V 75 110 ns
t
VALID,SO
SOMI output data valid time (Note 2)
U
C
L
K
e
d
g
e
t
o
S
O
M
I
v
a
l
i
d
,
C
L
=20pF
3V 50 75 ns
t
S
O
M
I
o
u
t
p
u
t
d
a
t
a
h
o
l
d
t
i
m
e
(
N
o
t
e
3
)
C
2
0
p
F
2.2 V 0 ns
t
HD,MO
SOMI output data hold time (Note 3) C
L
=20pF
3V 0 ns
NOTES: 1. f
UCxCLK
=
1
2t
LO∕HI
with t
LO∕HI
≥ max(t
VALID,MO(Master)
+ t
SU,SI(USCI),
t
SU,MI(Master)
+ t
VALID,SO(USCI)
).
For the master’s parameters t
SU,MI(Master)
and t
VALID,MO(Master)
refer to the SPI parameters of the attached master.
2. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 23 and Figure 24.
3. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Negative values indicate that the
data on the SOMI output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams
in Figure 23 and Figure 24.