Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 16-Bit 16 MHz I/O number 48

MSP430F261x

MSP430F241x

SLAS541K –JUNE 2007–REVISED NOVEMBER 2012

www.ti.com

Memory Organization

Table 8. Memory Organization

MSP430F2416 MSP430F2417 MSP430F2418 MSP430F2419

MSP430F2616 MSP430F2617 MSP430F2618 MSP430F2619

Memory Size 92KB 92KB 116KB 120KB

Main: interrupt vector Flash 0x0FFFF-0x0FFC0 0x0FFFF-0x0FFC0 0x0FFFF-0x0FFC0 0x0FFFF-0x0FFC0

Main: code memory Flash 0x18FFF-0x02100 0x19FFF-0x03100 0x1FFFF-0x03100 0x1FFFF-0x02100

RAM (total) Size 4KB 8KB 8KB 4KB

0x020FF-0x01100 0x030FF-0x01100 0x030FF-0x01100 0x020FF-0x01100

Extended Size 2KB 6KB 6KB 2KB

0x020FF-0x01900 0x030FF-0x01900 0x030FF-0x01900 0x020FF-0x01900

Mirrored Size 2KB 2KB 2KB 2KB

0x018FF-0x01100 0x018FF-0x01100 0x018FF-0x01100 0x018FF-0x01100

Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte

Flash 0x010FF-0x01000 0x010FF-0x01000 0x010FF-0x01000 0x010FF-0x01000

Boot memory Size 1KB 1KB 1KB 1KB

ROM 0x00FFF-0x00C00 0x00FFF-0x00C00 0x00FFF-0x00C00 0x00FFF-0x00C00

RAM (mirrored at Size 2KB 2KB 2KB 2KB

0x18FF to 0x01100) 0x009FF-0x00200 0x009FF-0x00200 0x009FF-0x00200 0x009FF-0x00200

Peripherals 16-bit 0x001FF-0x00100 0x001FF-0x00100 0x001FF-0x00100 0x001FF-0x00100

8-bit 0x000FF-0x00010 0x000FF-0x00010 0x000FF-0x00010 0x000FF-0x00010

8-bit SFR 0x0000F-0x00000 0x0000F-0x00000 0x0000F-0x00000 0x0000F-0x00000

Bootstrap Loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to

the MSP430 memory via the BSL is protected by a user-defined password. For complete description of the

features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader (BSL)

User's Guide (SLAU319).

Table 9. BSL Pin Functions

PM, PN PACKAGE ZQW PACKAGE

BSL FUNCTION

PINS PINS

Data Transmit 13 - P1.1 H1 - P1.1

Data Receive 22 - P2.2 M3 - P2.2

Flash Memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The

CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also

called information memory.

• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It

can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is

required.

• Flash content integrity check with marginal read modes