Datasheet

C
VREF+
1 µF
0
1 ms
10 ms
100 ms t
REFON
t
REFON
≈ .66 x C
VREF+
[ms] with C
VREF+
in µF
100 µF
10 µF
MSP430F261x
MSP430F241x
www.ti.com SLAS541K –JUNE 2007–REVISED NOVEMBER 2012
12-Bit ADC Built-In Reference
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS T
A
V
CC
MIN NOM MAX UNIT
-40°C to 85°C 2.4 2.5 2.6
REF2_5V = 1 for 2.5 V,
3 V
Positive built-in
I
VREF+
max ≤ I
VREF+
≤ I
VREF+
min
105°C 2.37 2.5 2.64
V
REF+
reference voltage V
-40°C to 85°C 1.44 1.5 1.56
REF2_5V = 0 for 1.5 V,
output
2.2 V, 3 V
I
VREF+
max ≤ I
VREF+
≤ I
VREF+
min
105°C 1.42 1.5 1.57
REF2_5V = 0, 2.2
I
VREF+
max ≤ I
VREF+
≤ I
VREF+
min
AV
CC
minimum
voltage, positive REF2_5V = 1, 2.8
AV
CC(min)
V
built-in reference -0.5 mA ≤ I
VREF+
≤ I
VREF+
min
active
REF2_5V = 1, 2.9
-1 mA ≤ I
VREF+
≤ I
VREF+
min
2.2 V 0.01 -0.5
Load current out of
I
VREF+
mA
V
REF+
terminal
3 V 0.01 -1
I
VREF+
= 500 µA ± 100 µA, 2.2 V ±2
Analog input voltage ≈ 0.75 V, LSB
Load-current 3 V ±2
REF2_5V = 0
I
L(VREF)+
regulation, V
REF+
I
VREF+
= 500 µA ± 100 µA,
terminal
(1)
Analog input voltage ≈ 1.25 V, 3 V ±2 LSB
REF2_5V = 1
Load current I
VREF+
= 100 µA → 900 µA,
I
DL(VREF) +
regulation, V
REF+
C
VREF+
= 5 µF, ax ≈ 0.5 × V
REF+
, 3 V 20 ns
terminal
(2)
Error of conversion result ≤ 1 LSB
Capacitance at pin REFON = 1,
C
VREF+
2.2 V, 3 V 5 10 µF
V
REF+
(3)
0 mA ≤ I
VREF+
≤ I
VREF+
max
Temperature
I
VREF+
is a constant in the range of
T
REF+
coefficient of built-in 2.2 V, 3 V ±100 ppm/°C
0 mA ≤ I
VREF+
≤ 1 mA
reference
(2)
Settle time of
internal reference I
VREF+
= 0.5 mA, C
VREF+
= 10 µF,
t
REFON
2.2 V 17 ms
voltage (see V
REF+
= 1.5 V, V
AVCC
= 2.2 V
Figure 38 )
(4) (2)
(1) Not production tested, limits characterized.
(2) Not production tested, limits verified by design.
(3) The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins V
REF+
and AV
SS
and V
REF-
/V
eREF-
and AV
SS
: 10 µF tantalum and 100 nF ceramic.
(4) The condition is that the error in a conversion started after t
REFON
is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
Figure 38. Typical Settling Time of Internal Reference t
REFON
vs External Capacitor on V
REF+
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