Datasheet

P5SEL.x
P5DIR.x
P5IN.x
Module X IN
Module X OUT
P5OUT.x
P5REN.x
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
Direction
0: Input
1: Output
D
EN
DVSS
DVCC
Pad Logic
1
1
0
1
0
1
0
MSP430F23x
MSP430F24x(1)
MSP430F2410
www.ti.com SLAS547I –JUNE 2007–REVISED DECEMBER 2012
Port P5 Pin Schematic: P5.4 to P5.7, Input/Output With Schmitt Trigger
Table 26. Port P5.4 to P5.7 Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P5.x) x FUNCTION
P5DIR.x P5SEL.x
P5.4 (I/O) I: 0; O: 1 0
P5.4/MCLK 4
MCLK 1 1
P5.5 (I/O) I: 0; O: 1 0
P5.5/SMCLK 5
SMCLK 1 1
P5.6 (I/O) I: 0; O: 1 0
P5.6/ACLK 6
ACLK 1 1
P5.7 (I/O) I: 0; O: 1 0
P5.7/TBOUTH/SVSOUT 7 Timer_B7.TBOUTH 0 1
SVSOUT 1 1
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 75