Datasheet

MSP430F261x
MSP430F241x
SLAS541K –JUNE 2007–REVISED NOVEMBER 2012 www.ti.com
Timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 13. Timer_B3, Timer_B7 Signal Connections
INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER
DEVICE INPUT MODULE MODULE
OUTPUT
SIGNAL INPUT NAME BLOCK
ZQW PM, PN PM, PN ZQW
SIGNAL
K11 - P4.7 43 - P4.7 TBCLK TBCLK Timer NA
ACLK ACLK
SMCLK SMCLK
K11 - P4.7 43 - P4.7 TBCLK INCLK
M9 - P4.0 36 - P4.0 TB0 CCI0A CCR0 TB0 36 - P4.0 M9 - P4.0
M9- P4.0 36 - P4.0 TB0 CCI0B ADC12
(internal)
DV
SS
GND
DV
CC
V
CC
J9 - P4.1 37 - P4.1 TB1 CCI1A CCR1 TB1 37 - P4.1 J9 - P4.1
J9 - P4.1 37 - P4.1 TB1 CCI1B ADC12
(internal)
DV
SS
GND
DV
CC
V
CC
M10 - P4.2 38 - P4.2 TB2 CCI2A CCR2 TB2 38 - P4.2 M10 - P4.2
M10 - P4.2 38 - P4.2 TB2 CCI2B DAC_0
(internal)
DV
SS
GND DAC_1
(internal)
DV
CC
V
CC
L10 - P4.3 39 - P4.3 TB3 CCI3A CCR3 TB3 39 - P4.3 L10 - P4.3
L10 - P4.3 39 - P4.3 TB3 CCI3B
DV
SS
GND
DV
CC
V
CC
M11 - P4.4 40 - P4.4 TB4 CCI4A CCR4 TB4 40 - P4.4 M11 - P4.4
M11 - P4.4 40 - P4.4 TB4 CCI4B
DV
SS
GND
DV
CC
V
CC
M12 - P4.5 41 - P4.5 TB5 CCI5A CCR5 TB5 41 - P4.5 M12 - P4.5
M12 - P4.5 41 - P4.5 TB5 CCI5B
DV
SS
GND
DV
CC
V
CC
L12 - P4.6 42 - P4.6 TB6 CCI6A CCR6 TB6 42 - P4.6 L12 - P4.6
ACLK (internal) CCI6B
DV
SS
GND
DV
CC
V
CC
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