Datasheet

MSP430F23x0
www.ti.com SLAS518E –AUGUST 2006– REVISED AUGUST 2011
Table 17. Peripherals With Byte Access (continued)
ADDRESS
MODULE REGISTER NAME SHORT NAME
OFFSET
USCI_A0 USCI_A0 transmit buffer UCA0TXBUF 0x0067
USCI_A0 receive buffer UCA0RXBUF 0x0066
USCI_A0 status UCA0STAT 0x0065
USCI_A0 modulation control UCA0MCTL 0x0064
USCI_A0 baud rate control 1 UCA0BR1 0x0063
USCI_A0 baud rate control 0 UCA0BR0 0x0062
USCI_A0 control 1 UCA0CTL1 0x0061
USCI_A0 control 0 UCA0CTL0 0x0060
USCI_A0 IrDA receive control UCA0IRRCTL 0x005F
USCI_A0 IrDA transmit control UCA0IRTCTL 0x005E
USCI_A0 auto baud rate control UCA0ABCTL 0x005D
Basic Clock System+ Basic clock system control 3 BCSCTL3 0x0053
Basic clock system control 2 BCSCTL2 0x0058
Basic clock system control 1 BCSCTL1 0x0057
DCO clock frequency control DCOCTL 0x0056
Port P4 Port P4 resistor enable P4REN 0x0011
Port P4 selection P4SEL 0x001F
Port P4 direction P4DIR 0x001E
Port P4 output P4OUT 0x001D
Port P4 input P4IN 0x001C
Port P3 Port P3 resistor enable P3REN 0x0010
Port P3 selection P3SEL 0x001B
Port P3 direction P3DIR 0x001A
Port P3 output P3OUT 0x0019
Port P3 input P3IN 0x0018
Port P2 Port P2 resistor enable P2REN 0x002F
Port P2 selection P2SEL 0x002E
Port P2 interrupt enable P2IE 0x002D
Port P2 interrupt edge select P2IES 0x002C
Port P2 interrupt flag P2IFG 0x002B
Port P2 direction P2DIR 0x002A
Port P2 output P2OUT 0x0029
Port P2 input P2IN 0x0028
Port P1 Port P1 resistor enable P1REN 0x0027
Port P1 selection P1SEL 0x0026
Port P1 interrupt enable P1IE 0x0025
Port P1 interrupt edge select P1IES 0x0024
Port P1 interrupt flag P1IFG 0x0023
Port P1 direction P1DIR 0x0022
Port P1 output P1OUT 0x0021
Port P1 input P1IN 0x0020
Special Function SFR interrupt flag 2 IFG2 0x0003
SFR interrupt flag 1 IFG1 0x0002
SFR interrupt enable 2 IE2 0x0001
SFR interrupt enable 1 IE1 0x0000
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