Datasheet

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SLAS439A − SEPTEMBER 2004 − REVISED JUNE 2005
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
device pinout
RGE PACKAGE
(TOP VIEW)
DW, PW, or DGV PACKAGE
(TOP VIEW)
Note: NC pins not internally connected
Power Pad connection to V
SS
recommended
10
1
9
7
8
6
5
4
3
2
11
20
12
14
13
15
16
17
18
19
TEST
V
CC
P2.5/CA5
V
SS
XOUT/P2.7/CA7
XIN/P2.6/CA6
RST
/NMI
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2/CA1
P2.3/TA1/CA0
P1.4/SMCLK/TCK
1
6
5
4
3
2
18
13
14
15
16
17
712111098
1924 23 22 21 20
TEST
V
CC
P2.5/CA5
V
SS
XOUT/P2.7/CA7
XIN/P2.6/CA6
RST/NMI
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2/CA1 P2.3/TA1/CA0
P1.4/SMCLK/TCK
NC
NC NC
NC
functional block diagram
ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN XOUT
P2 & XT1
MDB, 16 Bit
MAB, 16 Bit
MCLK
MAB,
4 Bit
V
CC
V
SS
RST/NMI
P1 & JTAG
8KB Flash
4KB Flash
2KB Flash
1KB Flash
256B RAM
256B RAM
128B RAM
128B RAM
Watchdog
Timer+
15/16-Bit
Timer_A3
3 CC Reg
POR/
Brownout
Comparator
A+
8 channel
input mux
8 8
MDB, 8 Bit
MDB, 16-Bit
Test
JTAG
MAB, 16-Bit
Emulation
Module (2BP)
TEST
I/O Port 2
8 I/Os, with
Interrupt
Capability &
pull-up/down
resistors
Basic
Clock
I/O Port 1
8 I/Os, with
Interrupt
Capability &
pull-up/down
resistors
NOTE: See port schematics section for detailed I/O information.