Datasheet

MSP430F21x2
www.ti.com SLAS578J –NOVEMBER 2007– REVISED JANUARY 2012
Timer1_A2
Timer1_A2 is a 16-bit timer/counter with two capture/compare registers. Timer1_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 15. Timer1_A2 Signal Connections
INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER
DEVICE INPUT MODULE MODULE
OUTPUT
SIGNAL INPUT NAME BLOCK
PW RHB, RTV PW RHB, RTV
SIGNAL
21 - P1.0 21 - P1.0 TACLK TACLK Timer NA
ACLK ACLK
SMCLK SMCLK
9 - P2.1 7 - P2.1 TAINCLK INCLK
22 - P1.1 22 - P1.1 TA0 CCI0A CCR0 TA0 17 - P3.6 15 - P3.6
17 - P3.6 15 - P3.6 TA0 CCI0B
DV
SS
GND
DV
CC
V
CC
18 - P3.7 16 - P3.7 TA1 CCI1A CCR1 TA1 18 - P3.7 16 - P3.7
CAOUT
CCI1B
(internal)
DV
SS
GND
DV
CC
V
CC
Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART,
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
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