Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VQFN 24 (4x4) 16-Bit 16 MHz I/O number 16

MSP430F21x1

www.ti.com

SLAS439F –SEPTEMBER 2004– REVISED AUGUST 2011

MIXED SIGNAL MICROCONTROLLER

FEATURES

• Serial Onboard Programming, No External

Programming Voltage Needed, Programmable

• Low Supply Voltage Range: 1.8 V to 3.6 V

Code Protection by Security Fuse

• Ultra-Low Power Consumption

• Bootstrap Loader

– Active Mode: 250 μA at 1 MHz, 2.2 V

• On Chip Emulation Module

– Standby Mode: 0.7 μA

• Family Members:

– Off Mode (RAM Retention): 0.1 μA

– MSP430F2101

• Ultra-Fast Wake-Up From Standby Mode in

– 1KB + 256B Flash Memory

Less Than 1 μs

– 128B RAM

• 16-Bit RISC Architecture, 62.5-ns Instruction

– MSP430F2111

Cycle Time

– 2KB + 256B Flash Memory

• Basic Clock Module Configurations

– 128B RAM

– Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1%

– MSP430F2121

– 32-kHz Crystal

– 4KB + 256B Flash Memory

– High-Frequency Crystal up to 16 MHz

– 256B RAM

– Resonator

– MSP430F2131

– External Digital Clock Source

– 8KB + 256B Flash Memory

• 16-Bit Timer_A With Three Capture/Compare

– 256B RAM

Registers

• Available in a 20-Pin Plastic Small-Outline

• On-Chip Comparator for Analog Signal

Wide Body (SOWB) Package, 20-Pin Plastic

Compare Function or Slope Analog-to-Digital

Small-Outline Thin (TSSOP) Package, 20-Pin

(A/D) Conversion

TVSOP Package, and 24-Pin QFN Package

• Brownout Detector

• For Complete Module Descriptions, See the

MSP430x2xx Family User’s Guide (SLAU144)

DESCRIPTION

The Texas Instruments MSP430 family of ultra-low-power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code

efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less

than 1 μs.

The MSP430x21x1 series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer, versatile

analog comparator, and sixteen I/O pins.

Typical applications include sensor systems that capture analog signals, convert themto digital values, and then

process the data for display or for transmission to a host system. Stand-alone RF sensor front end is another

area of application. The analog comparator provides slope A/D conversion capability.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (60 pages)

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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • • • Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 250 μA at 1 MHz, 2.2 V – Standby Mode: 0.7 μA – Off Mode (RAM Retention): 0.1 μA Ultra-Fast Wake-Up From Standby Mode in Less Than 1 μs 16-Bit RISC Architecture, 62.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Table 1.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Device Pinout DW, PW, or DGV PACKAGE (TOP VIEW) TEST VCC P2.5/CA5 VSS XOUT/P2.7/CA7 XIN/P2.6/CA6 RST/NMI P2.0/ACLK/CA2 P2.1/INCLK/CA3 P2.2/CAOUT/TA0/CA4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2/CA1 P2.3/TA1/CA0 P2.5/CA5 VCC TEST P1.7/TA2/TDO/TDI P1.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Functional Block Diagram VCC VSS P1.x, JTAG 8 P2.x, XIN/XOUT 8 XOUT XIN Basic Clock System+ ACLK SMCLK MCLK 16MHz CPU incl.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Table 2. Terminal Functions TERMINAL NO. DW, PW, or DGV RGE P1.0/TACLK 13 13 I/O P1.1/TA 14 14 I/O P1.2/TA1 15 15 I/O P1.3/TA2 16 16 I/O P1.4/SMCLK/TCK 17 17 I/O P1.5/TA/TMS 18 18 I/O P1.6/TA1/TDI/TCLK 19 20 I/O P1.7/TA2/TDO/TDI (1) 20 21 I/O P2.0/ACLK/CA2 8 6 I/O P2.1/INCLK/CA3 9 7 I/O P2.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
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MSP430F21x1 www.ti.com SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 Operating Modes The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: • Active mode (AM) – All clocks are active.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up. Table 5.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw rw-0, 1 rw-(0), (1) Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Memory Organization Table 10.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 14. Timer_A3 Signal Connections INPUT PIN NUMBER DW, PW, DGV RGE DEVICE INPUT SIGNAL 13 - P1.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Peripheral File Map Table 15.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS Voltage applied to any pin -0.3 V to 4.1 V (2) -0.3 V to (VCC + 0.3 V) ±2 mA Diode current at any device terminal Storage temperature, Tstg (1) (3) Unprogrammed device -55°C to 150°C Programmed device -55°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Active Mode Supply Current (into DVCC + AVCC ) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER IAM,1MHz IAM,1MHz IAM,4kHz IAM,100kHz (1) (2) TEST CONDITIONS TA VCC MIN TYP MAX 2.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ILPM0,1MHz ILPM0,100kHz ILPM2 TEST CONDITIONS TA VCC 65 80 Low-power mode 0 (LPM0) current (3) 3V 85 100 2.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Schmitt-Trigger Inputs (Ports P1, P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIT+ TEST CONDITIONS Positive-going input threshold voltage VCC Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ - VIT- ) RPull Pullup/pulldown resistor For pullup: VIN = VSS, For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC TYP MAX 0.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Outputs (Ports P1, P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IOH(max) = -1.5 mA VOH High-level output voltage 2.2 V IOH(max) = -6 mA (2) IOH(max) = -1.5 mA (1) 3V IOH(max) = -6 mA (2) IOL(max) = 1.5 mA VOL Low-level output voltage (2) MIN MAX VCC - 0.25 VCC VCC - 0.6 VCC VCC - 0.25 VCC VCC - 0.6 VCC VSS VSS + 0.25 (1) 2.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Typical Characteristics - Outputs One output loaded at a time. TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P2.4 TA = 25°C 20.0 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 25.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P2.4 40.0 TA = 85°C 30.0 20.0 10.0 0.0 0.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Calibrated DCO Frequencies - Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25°C 3V -1 ±0.2 +1 25°C 3V 0.990 1 1.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25°C 8-MHz tolerance over VCC 25°C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 ±2 +3 % 1.8 V to 3.6 V -3 ±2 +3 % 25°C 2.2 V to 3.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Typical Characteristics - Calibrated 1-MHz DCO Frequency CALIBRATED 1-MHz FREQUENCY vs TEMPERATURE CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE 1.03 1.03 1.02 1.02 1.00 VCC = 3 V VCC = 2.2 V 0.99 Frequency – MHz Frequency – MHz VCC = 1.8 V 1.01 1.01 TA = 105°C TA = 85°C 1.00 TA = 25°C 0.99 VCC = 3.6 V TA = -40°C 0.98 0.97 -50 0.98 -25 0 25 50 TA – Temperature – °C Figure 11.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Wake-Up From Lower-Power Modes (LPM3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 (1) (2) UNIT 2 BCSCTL1 = CALBC1_8MHZ, DCO clock wake-up time DCOCTL = CALDCO_8MHZ from LPM3/4 (1) BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ 2.2 V/3 V 1.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Crystal Oscillator LFXT1, High-Frequency Mode (1) PARAMETER VCC MIN XTS = 1, LFXT1Sx = 0 1.8 V to 3.6 V LFXT1 oscillator crystal frequency, HF mode 1 XTS = 1, LFXT1Sx = 1 LFXT1 oscillator crystal frequency, HF mode 2 XTS = 1, LFXT1Sx = 2 fLFXT1,HF0 LFXT1 oscillator crystal frequency, HF mode 0 fLFXT1,HF1 fLFXT1,HF2 TEST CONDITIONS MAX UNIT 0.4 1 MHz 1.8 V to 3.6 V 1 4 MHz 1.8 V to 3.6 V 2 10 2.2 V to 3.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1) OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C 800 100000 LFXT1Sx = 3 XT Oscillator Supply Current – µA Oscillation Allowance – W 700 10000 1000 LFXT1Sx = 3 100 LFXT1Sx = 1 LFXT1Sx = 2 600 500 400 300 LFXT1Sx = 2 200 100 LFXT1Sx = 1 10 0.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTA Timer_A clock frequency Internal: SMCLK, ACLK External: TACLK, INCLK Duty cycle = 50% ± 10% tTA,cap Timer_A capture timing TA0, TA1, TA2 VCC MIN TYP MAX 2.2 V 10 3V 16 2.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com 0V VCC 0 1 CAF CAON To Internal Modules Low-Pass Filter + _ V+ V− 0 0 1 1 CAOUT Set CAIFG Flag τ ≈ 2.0 µs Figure 16. Comparator_A+ Module Block Diagram VCAOUT Overdrive V− 400 mV t (response) V+ Figure 17. Overdrive Definition CASHORT CA0 CA1 1 VIN + − Comparator_A+ CASHORT = 1 IOUT = 10µA Figure 18.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Typical Characteristics - Comparator_A+ V(RefVT) vs TEMPERATURE VCC = 2.2 V V(RefVT) vs TEMPERATURE VCC = 2.2 V 650 650 VCC = 2.2 V 600 V(REFVT) – Reference Volts – mV V(REFVT) – Reference Volts – mV VCC = 3 V Typical 550 500 450 400 -45 -25 15 55 75 35 -5 TA – Free-Air Temperature – °C 600 Typical 550 500 450 400 -45 95 -25 15 55 75 35 -5 TA – Free-Air Temperature – °C Figure 19. Figure 20.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC (PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 3 5 mA IERASE Supply current from VCC during erase 2.2 V/3.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 P1OUT.x 0 1 0 1 1 Direction 0: Input 1: Output 1 Module XOUT DVSS DVCC P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1SEL.x P1IN.x EN Module XIN D P1IE.x P1IRQ.x EN Q P1IFG.x P1SEL.x P1IES.x Set Interrupt Edge Select Table 17. Port P1 (P1.0 to P1.3) Pin Functions PIN NAME (P1.x) x FUNCTION P1.0 P1.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.1 P1DIR.1 0 P1OUT.1 0 1 0 1 1 Direction 0: Input 1: Output 1 Module XOUT DVSS DVCC P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI P1.7/TA2/TDO/TDI Bus Keeper P1SEL.1 EN P1IN.1 EN Module XIN D P1IE.1 P1IRQ.1 EN Q P1IFG.1 P1SEL.1 P1IES.1 Set Interrupt Edge Select To JTAG From JTAG TDO From JTAG P1.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Table 18. Port P1 (P1.4 to P1.7) Pin Functions PIN NAME (P1.x) x FUNCTION P1.4 P1.4/SMCLK/TCK 4 (2) (I/O) 5 P1.7/TA2/TDO/TDI (1) (2) (3) 36 6 7 P1SEL.x TEST I: 0; O: 1 0 0 1 1 0 TCK X X 1 I: 0; O: 1 0 0 Timer_A3.TA0 1 1 0 TMS X X 1 I: 0; O: 1 0 0 P1.6 (2) (I/O) P1.6/TA1/TDI/TCLK P1DIR.x SMCLK P1.5 (2) (I/O) P1.5/TA0/TMS CONTROL BITS / SIGNALS (1) Timer_A3.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x P2REN.x P2DIR.x 0 0 Module XOUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS P2.0/ACLK/CA2 P2.1/INCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/TA1/CA0 P2.4/TA2/CA1 P2.5/CA5 Bus Keeper P2SEL.x EN P2IN.x EN Module XIN D P2IE.x P2IRQ.x EN Q Set P2IFG.x P2SEL.x P2IES.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Table 20. Port P2 (P2.0 to P2.5) Pin Functions PIN NAME (P2.x) x FUNCTION P2.0 P2.0/ACLK/CA2 0 (2) (I/O) 1 2 3 0 0 1 0 CA2 (3) X X 1 I: 0; O: 1 0 0 Timer_A3.INCLK 0 1 0 DVSS 1 1 0 CA3 (3) X X 1 P2.5/CA5 (1) (2) (3) 38 4 5 (2) I: 0; O: 1 0 0 Timer_A3.CCI0B 0 1 0 CAOUT 1 1 0 (3) X X 1 P2.3 (2) (I/O) I: 0; O: 1 0 0 Timer_A3.TA1 1 1 0 CA0 (3) X X 1 P2.4 P2.4/TA2/CA1 CAPD.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 P2.7/XOUT/CA7 LFXT1 off 0 LFXT1CLK 1 P2SEL.7 P2REN.6 P2DIR.6 0 0 Module XOUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS P2.6/XIN/CA6 Bus Keeper P2SEL.6 EN P2IN.6 EN Module XIN D P2IE.6 P2IRQ.6 EN Q P2IFG.6 P2SEL.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Table 22. Port P2 (P2.6) Pin Functions PIN NAME (P2.x) x FUNCTION P2.6 (I/O) P2.6/XIN/CA6 (1) (2) (3) 40 6 CONTROL BITS / SIGNALS (1) P2DIR.x P2SEL.x CAPD.x I: 0; O: 1 0 0 XIN (2) X 1 0 CA6 (3) X X 1 X = don't care Default after reset (PUC/POR) Setting theCAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currentswhen applying analog signals.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 LFXT1 off 0 LFXT1CLK 1 From P2.6/XIN P2.6/XIN/CA6 Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module XOUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS P2.7/XOUT/CA7 Bus Keeper P2SEL.7 EN P2IN.7 EN Module XIN D P2IE.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com Table 24. Port P2 (P2.7) Pin Functions PIN NAME (P2.x) P2.7/XOUT/CA7 (1) (2) (3) (4) 42 x 6 FUNCTION CONTROL BITS / SIGNALS (1) P2DIR.x P2SEL.x CAPD.x P2.7 (I/O) I: 0; O: 1 0 0 XOUT (2) (3) X 1 0 CA7 (4) X X 1 X = don't care Default after reset (PUC/POR) If the pin XOUT/P2.7/CA7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this pin after reset.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned.
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MSP430F21x1 SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 www.ti.com REVISION HISTORY Literature Number Summary SLAS439 PRODUCT PREVIEW release SLAS439A PRODUCTION DATA release SLAS439B Corrected instruction cycle time to 62.5ns, pg 1. Updated Figure 1, pg 12. Updated Figures 2 and 3, pg 13. RPull unit corrected from Ω to kΩ, pg 15. MAX load current specification and Note 3 removed from "outputs" table, pg 16.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F2101IDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2101IRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2101IRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F2121TRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2121TRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2131IDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2131IRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2111IRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F2111IRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F2111TDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F2111TRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F2111TRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F2121IDGVR TVSOP DGV 20 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.