Datasheet

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005
76
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P2 (P2.6) pin schematics, MSP430x20x3
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.6
1
0
P2DIR.6
P2IN.6
P2IRQ.6
D
EN
Module X IN
1
0
Module X OUT
P2OUT.6
Interrupt
Edge
Select
Q
EN
Set
P2SEL.6
P2IES.6
P2IFG.6
P2.6/XIN/TA1
1
0
DVSS
DVCC
P2REN.6
Pad Logic
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
LFXT1 off
0
1
1
LFXT1CLK
P2SEL.7
P2IE.6
Port P2 (P2.6) pin functions, MSP430x20x3
PIN NAME (P2.X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x P2SEL.x
P2.6/XIN/TA1
6
P2.6 Input/Output 0/1 0
P2.6/XIN/TA1
6
XIN† (see Note 3) 0 1
Timer_A2.TA1 1 1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.