Datasheet

MSP430F20x3
MSP430F20x2
MSP430F20x1
www.ti.com SLAS491I –AUGUST 2005–REVISED DECEMBER 2012
Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 12. Timer_A2 Signal Connections (MSP430F20x1)
INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER
DEVICE INPUT MODULE MODULE
OUTPUT
SIGNAL INPUT NAME BLOCK
PW, N RSA PW, N RSA
SIGNAL
2 - P1.0 1 - P1.0 TACLK TACLK
ACLK ACLK
Timer NA
SMCLK SMCLK
2 - P1.0 1 - P1.0 TACLK INCLK
3 - P1.1 2 - P1.1 TA0 CCI0A 3 - P1.1 2 - P1.1
ACLK (internal) CCI0B 7 - P1.5 6 - P1.5
CCR0 TA0
V
SS
GND
V
CC
V
CC
4 - P1.2 3 - P1.2 TA1 CCI1A 4 - P1.2 3 - P1.2
CAOUT
CCI1B 8 - P1.6 7 - P1.6
(internal)
CCR1 TA1
V
SS
GND 13 - P2.6 12 - P2.6
V
CC
V
CC
Table 13. Timer_A2 Signal Connections (MSP430F20x2, MSP430F20x3)
INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER
DEVICE INPUT MODULE MODULE
OUTPUT
SIGNAL INPUT NAME BLOCK
PW, N RSA PW, N RSA
SIGNAL
2 - P1.0 1 - P1.0 TACLK TACLK Timer NA
ACLK ACLK
SMCLK SMCLK
2 - P1.0 1 - P1.0 TACLK INCLK
3 - P1.1 2 - P1.1 TA0 CCI0A CCR0 TA0 3 - P1.1 2 - P1.1
7 - P1.5 6 - P1.5 ACLK (internal) CCI0B 7 - P1.5 6 - P1.5
V
SS
GND
V
CC
V
CC
4 - P1.2 3 - P1.2 TA1 CCI1A CCR1 TA1 4 - P1.2 3 - P1.2
8 - P1.6 7 - P1.6 TA1 CCI1B 8 - P1.6 7 - P1.6
V
SS
GND 13 - P2.6 12 - P2.6
V
CC
V
CC
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