Datasheet

MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491I –AUGUST 2005–REVISED DECEMBER 2012 www.ti.com
10-Bit ADC, Built-In Voltage Reference (MSP430F20x2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
I
VREF+
≤ 1 mA, REF2_5V = 0 2.2
Positive built-in
V
CC,REF+
reference analog I
VREF+
≤ 0.5 mA, REF2_5V = 1 2.8 V
supply voltage range
I
VREF+
≤ 1 mA, REF2_5V = 1 2.9
I
VREF+
≤ I
VREF+
max, REF2_5V = 0 2.2 V, 3 V 1.41 1.5 1.59
Positive built-in
V
REF+
V
reference voltage
I
VREF+
≤ I
VREF+
max, REF2_5V = 1 3 V 2.35 2.5 2.65
2.2 V ±0.5
Maximum V
REF+
load
I
LD,VREF+
mA
current
3 V ±1
I
VREF+
= 500 µA ± 100 µA,
Analog input voltage V
Ax
≈ 0.75 V, 2.2 V, 3 V ±2
REF2_5V = 0
V
REF+
load regulation LSB
I
VREF+
= 500 µA ± 100 µA,
Analog input voltage V
Ax
≈ 1.25 V, 3 V ±2
REF2_5V = 1
I
VREF+
= 100 µA to 900 µA, ADC10SR = 0 400
V
REF+
load regulation V
Ax
≈ 0.5 x V
REF+
,
3 V ns
response time Error of conversion result
ADC10SR = 1 2000
≤1 LSB
Maximum capacitance I
VREF+
≤ ±1 mA,
C
VREF+
2.2 V, 3 V 100 pF
at pin V
REF+
(1)
REFON = 1, REFOUT = 1
Temperature I
VREF+
= constant with
T
CREF+
2.2 V, 3 V ±100 ppm/°C
coefficient 0 mA ≤ I
VREF+
≤ 1 mA
Settling time of internal I
VREF+
= 0.5 mA, REF2_5V = 0,
t
REFON
3.6 V 30 µs
reference voltage
(2)
REFON = 0 to 1
I
VREF+
= 0.5 mA, ADC10SR = 0 1
REF2_5V = 0,
2.2 V
REFON = 1,
ADC10SR = 1 2.5
REFBURST = 1
Settling time of
t
REFBURST
µs
reference buffer
(2)
I
VREF+
= 0.5 mA, ADC10SR = 0 2
REF2_5V = 1,
3 V
REFON = 1,
ADC10SR = 1 4.5
REFBURST = 1
(1) The capacitance applied to the internal buffer operational amplifier, if switched to terminal P1.4/SMCLK/A4/VREF+/VeREF+/TCK
(REFOUT = 1), must be limited; otherwise, the reference buffer may become unstable.
(2) The condition is that the error in a conversion started after t
REFON
or t
RefBuf
is less than ±0.5 LSB.
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