Datasheet

  
  
SLAS272F − JULY 2000 − REVISED JUNE 2004
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.0 to P4.6, input/output with Schmitt-trigger
P4.0/TB0 ..
P4IN.x
Module X IN
Pad Logic
EN
D
x: bit identifier, 0 to 6 for Port P4
P4OUT.x
P4DIR.x
P4SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1
Bus Keeper
TBOUTHiZ
P4.6/TB6
0: Input
1: Output
P5SEL.7
Module X IN
w
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x MODULE X OUT PnIN.x MODULE X IN
P4Sel.0 P4DIR.0 P4DIR.0 P4OUT.0 Out0 signal
†
P4IN.0 CCI0A / CCI0B
‡
P4Sel.1 P4DIR.1 P4DIR.1 P4OUT.1 Out1 signal
†
P4IN.1 CCI1A / CCI1B
‡
P4Sel.2 P4DIR.2 P4DIR.2 P4OUT.2 Out2 signal
†
P4IN.2 CCI2A / CCI2B
‡
P4Sel.3 P4DIR.3 P4DIR.3 P4OUT.3 Out3 signal
†
P4IN.3 CCI3A / CCI3B
‡
P4Sel.4 P4DIR.4 P4DIR.4 P4OUT.4 Out4 signal
†
P4IN.4 CCI4A / CCI4B
‡
P4Sel.5 P4DIR.5 P4DIR.5 P4OUT.5 Out5 signal
†
P4IN.5 CCI5A / CCI5B
‡
P4Sel.6 P4DIR.6 P4DIR.6 P4OUT.6 Out6 signal
†
P4IN.6 CCI6A
‡
†
Signal from Timer_B
‡
Signal to Timer_B
§
From P5.7