Datasheet

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SLAS272F − JULY 2000 − REVISED JUNE 2004
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timer_B7 (MSP430x14x and MSP430x14x1 Only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B3/B7 Signal Connections
†
Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number
43 - P4.7 TBCLK TBCLK
ACLK ACLK
Timer
NA
SMCLK SMCLK
Timer NA
43 - P4.7 TBCLK INCLK
36 - P4.0 TB0 CCI0A
36 - P4.0
36 - P4.0 TB0 CCI0B
CCR0
TB0
ADC12 (internal)
DV
SS
GND
CCR0 TB0
DV
CC
V
CC
37 - P4.1 TB1 CCI1A
37 - P4.1
37 - P4.1 TB1 CCI1B
CCR1
TB1
ADC12 (internal)
DV
SS
GND
CCR1 TB1
DV
CC
V
CC
38 - P4.2 TB2 CCI2A
38 - P4.2
38 - P4.2 TB2 CCI2B
CCR2
TB2
DV
SS
GND
CCR2 TB2
DV
CC
V
CC
39 - P4.3 TB3 CCI3A
39 - P4.3
39 - P4.3 TB3 CCI3B
CCR3
TB3
DV
SS
GND
CCR3 TB3
DV
CC
V
CC
40 - P4.4 TB4 CCI4A
40 - P4.4
40 - P4.4 TB4 CCI4B
CCR4
TB4
DV
SS
GND
CCR4 TB4
DV
CC
V
CC
41 - P4.5 TB5 CCI5A
41 - P4.5
41 - P4.5 TB5 CCI5B
CCR5
TB5
DV
SS
GND
CCR5 TB5
DV
CC
V
CC
42 - P4.6 TB6 CCI6A
42 - P4.6
ACLK (internal) CCI6B
CCR6
TB6
DV
SS
GND
CCR6 TB6
DV
CC
V
CC
†
Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).