Datasheet

 
 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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DAC Low Byte (DACL)
7 6 5 4 3 2 1 0 Reset Value
SFR B5h 00h
DACL7−0 Least Significant Byte Register for DAC0−3, DAC Control (0 and 2), and DAC Load Control .
bits 7−0
NOTE: DAC2 and DAC3 available only on the MSC1211 and MSC1212.
DAC High Byte (DACH)
7 6 5 4 3 2 1 0 Reset Value
SFR B6h 00h
DACH7−0 Most Significant Byte Register for DAC0−3 and DAC Control (1 and 3).
bits 7−0
NOTE: DAC2 and DAC3 available only on the MSC1211 and MSC1212.
DAC Select (DACSEL)
7 6 5 4 3 2 1 0 Reset Value
SFR B7h DSEL7 DSEL6 DSEL5 DSEL4 DSEL3 DSEL2 DSEL1 DSEL0 00h
DSEL7−0 DAC Select and DAC Control Select. The DACSEL register selects which DAC output register or which DAC
bits 7−0 control register is accessed by the DACL and DACH registers.
DACSEL (B7h)
DACH (B6h)
DACL (B5h)
RESET VALUE
00h DAC0 (high) DAC0 (low) 0000h
01h DAC1 (high) DAC1 (low) 0000h
02h DAC2
(1)
(high) DAC2
(1)
(low) 0000h
03h DAC3
(1)
(high) DAC3
(1)
(low) 0000h
04h DACCON1 DACCON0 6363h
05h DACCON3
(1)
DACCON2
(1)
0303h
06h — LOADCON −−00h
07h — — —
(1)
DAC2 and DAC3 available only on the MSC1211 and MSC1212.