Datasheet

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 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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Port 2 Data Direction Low (P2DDRL)
7 6 5 4 3 2 1 0 Reset Value
SFR B1h P23H P23L P22H P22L P21H P21L P20H P20L 00h
P2.3 Port 2 Bit 3 Control.
bits 7−6
P23H P23L
0 0 Standard 8051 (Pull-Up)
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P2.2 Port 2 Bit 2 Control.
bits 5−4
P22H P22L
0 0 Standard 8051 (Pull-Up)
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P2.1 Port 2 Bit 1 Control.
bits 3−2
P21H P21L
0 0 Standard 8051 (Pull-Up)
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P2.0 Port 2 Bit 0 Control.
bits 1−0
P20H P20L
0 0 Standard 8051 (Pull-Up)
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.EGP23.