Datasheet

0 1.0
2.0
_
3.0
_
4.0
_
5.0
_
CAP VALUE (% OF NOM. 1 PF)
DC BIAS (V)
100%
80%
60%
40%_
20%
_
0402, 6.3V, X5R
0603, 10V, X5R
LP3985
www.ti.com SNVS087AC –OCTOBER 2000–REVISED MAY 2013
condition the capacitance value may drop below the minimum capacitance value given in the recommended
capacitor table (0.7µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case
size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers'
specifications for the nominal value capacitor are consulted for all conditions as some capacitor sizes (e.g. 0402)
may not be suitable in the actual application.
Figure 43. Graph Showing A Typical Variation in Capacitance vs DC Bias
The ceramic capacitor's capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R
has a similar tolerance over a reduced temperature range of −55°C to +85°C. Most large value ceramic
capacitors (≊ 2.2µF) are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop
by more than 50% as the temperature goes from 25°C to 85°C. Therefore X7R is recommended over Z5U and
Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 1µF to 4.7µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.
NOISE BYPASS CAPACITOR
Connecting a 0.01µF capacitor between the C
BYPASS
pin and ground significantly reduces noise on the regulator
output. This cap is connected directly to a high impedance node in the band gap reference circuit. Any significant
loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current
through this pin must be kept as low as possible for best output voltage accuracy.
The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic
capacitors with either NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate
film capacitors are available in small surface-mount packages and typically have extremely low leakage current.
Unlike many other LDO's, addition of a noise reduction capacitor does not effect the load transient response of
the device.
NO-LOAD STABILITY
The LP3985 will remain stable and in regulation with no external load. This is specially important in CMOS RAM
keep-alive applications.
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