Datasheet

LP3972
www.ti.com SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
Bit 7 6 5 4 3 2 1 0
Reset Value 1 0 1 0 1 0 1 0
Buck3:2 Voltage Ramp Control Register (B3RC) 8h’87 Definitions
Bit Access Name Description
7:4 R/W B3RR Data Code Ramp Rate mV/µS
4h’0 Instant
4h’1 1
4h’2 2
4h’3 3
4h’4 4
4h’5 5
4h’6 6
4h’7 7
4h’8 8
4h’9 9
4h’A 10
3:0 R/W B2RR Data Code Ramp Rate mV/µS
4h’0 Instant
4h’1 1
4h’2 2
4h’3 3
4h’4 4
4h’5 5
4h’6 6
4h’7 7
4h’8 8
4h’9 9
4h’A 10
INTERRUPT STATUS REGISTER ISRA
This register specifies the status bits for the interrupts generated by the PMIC. Thermal warning of the IC,
GPIO1, GPIO2, PWR_ON pin, TEST_JIG factory programmable on signal, and the SPARE pin.
Interrupt Status Register ISRA 8h’88
Bit 7 6 5 4 3 2 1 0
Designation Reserved T125 GPI2 GPI1 WUP3 WUP2 WUPT WUPS
Reset Value 0 0 0 0 0 0 0 0
Interrupt Status Register ISRA 8h’88 Definitions
Bit Access Name Description
7 — — Reserved
6 R T125 Status bit for thermal warning PMIC T>125C
0 = PMIC Temp. < 125°C
1 = PMIC Temp. > 125°C
5 R GPI2 Status bit for the input read in from GPIO 2 when set as Input
0 = GPI2 Logic Low
1 = GPI2 Logic High
4 R GPI1 Status bit for the input read in from GPIO 1 when set as Input
0 = GPI1 Logic Low
1 = GPI1 Logic High
3 R WUP3 PWR_ON Pin long pulse Wake Up Status
0 = No wake up event
1 = Long pulse wake up event
2 R WUP2 PWR_ON Pin Short pulse Wake Up Status
0 = No wake up event
1 = Short pulse wake up event
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