Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positivbe, adjustable SO 8 PowerPad

LP38511-ADJ

SNVS545D –JANUARY 2009–REVISED APRIL 2013

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SETTING THE OUTPUT VOLTAGE

The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the

formula:

OUT

= V

ADJ

x (1 + (R1/R2)) (1)

The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature

coefficients. It is important to remember that, although the value of V

ADJ

is specified, the final value of V

OUT

not. The use of low quality resistors for R1 and R2 can easily produce a V

OUT

value that is unacceptable.

It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 1.00 kΩ.

This is to reduce the possibility of any internal parasitic capacitances on the ADJ pin from creating an

undesirable phase shift that may interfere with device stability.

( (R1 x R2) / (R1 + R2) ) ≤ 1.00 kΩ (2)

FEED FORWARD CAPACITOR, C

When using a ceramic capacitor for C

OUT

, the typical ESR value will be too small to provide any meaningful

positive phase compensation, F

, to offset the internal negative phase shifts in the gain loop.

= 1 / (2 x π x C

OUT

x ESR) (3)

A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient

response of the device. This capacitor, C

, in parallel with R1, will form a zero in the loop response given by the

formula:

= 1 / (2 x π x C

x R1) (4)

For optimum load transient response select C

so the zero frequency, F

, falls between 20 kHz and 40 kHz.

= 1 / (2 x π x R1 x F

) (5)

The phase lead provided by C

diminishes as the DC gain approaches unity, or V

OUT

approaches V

ADJ

. This is

because C

also forms a pole with a frequency of:

= 1 / (2 x π x C

x (R1 || R2) ) (6)

It's important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far

apart in frequency. At lower output voltages the frequency of the pole and the zero mover closer together. The

phase lead provided from C

diminishes quickly as the output voltage is reduced, and has no effect when V

OUT

= V

ADJ

. For this reason, relying on this compensation technique alone is adequate only for higher output

voltages.

Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%

capacitor values for C

, for a range of V

OUT

values. Other values of R1, R2, and C

are available that will give