Datasheet

R
1
LP2995
+
+
V
DDQ
V
DD
V
TT
V
REF
V
TT
PV
IN
V
DDQ
V
REF
GND
AV
IN
V
SENSE
C
OUT
C
IN
R
2
V
TT
LP2995
PV
IN
V
DDQ
V
REF
GND
AV
IN
C
OUT
+
V
SENSE
+
V
DDQ
V
DD
V
TT
V
REF
C
IN
R
Vddq
LP2995
www.ti.com SNVS190M –FEBRUARY 2002–REVISED MARCH 2013
For SSTL-3 and other applications it may be desirable to change internal reference voltage scaling from VDDQ *
0.5. An external resistor in series with the VDDQ pin can be used to lower the reference voltage. Internally two
50 kΩ resistors set the output V
TT
to be equal to VDDQ * 0.5. The addition of a 11.1 kΩ external resistor will
change the internal reference voltage causing the two outputs to track VDDQ * 0.45. An implementation of this
circuit can be seen in Figure 18.
Figure 18. SSTL-3 Implementation
Another application that is sometimes required is to increase the V
TT
output voltage from the scaling factor of
VDDQ * 0.5. This can be accomplished independently of V
REF
by using a resistor divider network between V
TT
,
V
SENSE
and Ground. An example of this circuit can be seen in Figure 19.
Figure 19.
PCB Layout Considerations
1. AVIN and PVIN should be tied together for optimal performance. A local bypass capacitor should be placed
as close as possible to the PVIN pin.
2. GND should be connected to a ground plane with multiple vias for improved thermal performance.
3. V
SENSE
should be connected to the V
TT
termination bus at the point where regulation is required. For
motherboard applications an ideal location would be at the center of the termination bus.
4. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides
the most accurate point for creating the reference voltage.
5. V
REF
should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the V
REF
pin.
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