Datasheet

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LOG104
2
SBOS243C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage, V+ to V– .................................................................... 36V
Input Voltage ....................................................... V– (–0.5) to V+ (+0.5V)
Input Current ................................................................................... ±10mA
Output Short-Circuit
(2)
.............................................................. Continuous
Operating Temperature ....................................................–40°C to +85°C
Storage Temperature ..................................................... –55°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) Short-circuit to ground.
PIN DESCRIPTION
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, T
A
= –5°C to +75°C.
At T
A
= +25°C, V
S
= ±5V, R
OUT
= 10kΩ, unless otherwise noted.
Top View SO
I
2
NC
GND
V–
NC = No Internal Connection
LOG104
I
1
NC
V
OUT
V+
8
7
6
5
1
2
3
4
LOG104AID
PARAMETER CONDITION MIN TYP MAX UNITS
CORE LOG FUNCTION
I
IN
/V
OUT
Equation V
O
= (0.5V)log (I
1
/I
2
)V
LOG CONFORMITY ERROR
(1)
Initial 1nA to 100µA (5 decades) 0.01 0.2 %
100pA to 3.5mA (7.5 decades) 0.06 %
over Temperature 1nA to 100
µA (5 decades) 0.0001 %/°C
100pA to 3.5mA (7.5 decades)
(2)
0.0005 %/°C
GAIN
(3)
Initial Value 1nA to 100µA 0.5 V/decade
Gain Error 1nA to 100µA 0.15 ±1%
vs Temperature T
MIN
to T
MAX
0.003 0.01 %/°C
INPUT, A1 and A2
Offset Voltage ±0.3 ±1.5 mV
vs Temperature T
MIN
to T
MAX
±2 µV/°C
vs Power Supply (PSRR) V
S
= ±4.5V to ±18V 5 50 µV/V
Input Bias Current ±5pA
vs Temperature T
MIN
to T
MAX
Doubles Every 10°C
Voltage Noise f = 10Hz to 10kHz 3 µVrms
f = 1kHz 30 nV/√Hz
Current Noise f = 1kHz 4 fA/√Hz
Common-Mode Voltage Range (Positive) (V+) – 2 (V+) – 1.5 V
(Negative) (V–) + 2 (V–) + 1.2 V
Common-Mode Rejection Ratio (CMRR) 105 dB
OUTPUT, A2 (V
OUT
)
Output Offset, V
OSO
, Initial ±3 ±15 mV
vs Temperature T
MIN
to T
MAX
±2 µV/°C
Full-Scale Output (FSO) V
S
= ±5V (V–) + 1.2 (V+) – 1.5 V
Short-Circuit Current ±18 mA
PACKAGE PACKAGE
PRODUCT PACKAGE-LEAD DESIGNATOR MARKING
LOG104AID SO-8 D LOG104
NOTES: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
PACKAGE/ORDERING INFORMATION
(1)