Datasheet

LMZ31506

www.ti.com

SNVS993 –JUNE 2013

VIN and PVIN Input Voltage

The LMZ31506 allows for a variety of applications by using the VIN and PVIN pins together or separately. The

VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the

power converter system.

If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 14.5 V. If using the

VIN pin separately from the PVIN pin, the VIN pin must be between 4.5 V and 14.5 V, and the PVIN pin can

range from as low as 1.6 V to 14.5 V. A voltage divider connected to the INH/UVLO pin can adjust the either

input voltage UVLO appropriately. See the Programmable Undervoltage Lockout (UVLO) section of this

datasheet for more information.

3.3-V Input Operation

Applications operating from 3.3 V must provide at least 4.5 V for VIN. See application note, SLVA561 for help

creating 5 V from 3.3 V using a small, simple charge pump device.

Power Good (PWRGD)

The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 94% and 106% of the

set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is

between 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once

VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current

sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the voltage on SENSE+ is

lower than 91% or greater than 109% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input

UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V.

Product Folder Links: LMZ31506