Datasheet

LMH0031
www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013
Example: Program, via the AD port, I/O port bit 0 as output for the CRC Luma Error bit in the control registers.
1. Set ANC/CTRL to a logic-low.
2. Set RD/WR to a logic-low.
3. Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG register address.
4. Toggle A
CLK
.
5. Present 310h to AD[9:0] as the register data, the bit address of the CRC Luma Error bit in the control
registers.
6. Toggle A
CLK
.
Table 6. Control Register Bit, Pin[n] SEL[5:0] Codes for I/O Port Pin Mapping
(1)
Pin[n] SEL[5:0] Codes
I/P or
Register Bit Power-On Status
O/P
[5] [4] [3] [2] [1] [0] HEX
reserved 0 0 0 0 0 0 00 O/P
FF Flag Error 0 0 0 0 0 1 01 O/P
AP Flag Error 0 0 0 0 1 0 02 O/P
ANC Flag Error 0 0 0 0 1 1 03 O/P
CRC Error (SD/HD) 0 0 0 1 0 0 04 O/P I/O Port Bit 5
Addresses 05h and 06h are reserved
ANC FIFO 90% FULL 0 0 0 1 1 1 07 O/P
SHORT MSG DETECT 0 0 1 0 0 0 08 O/P
FULL MSG AVAIL 0 0 1 0 0 1 09 O/P
Addresses 0Ah through 0Ch are reserved
SAV 0 0 1 1 0 1 0D O/P
EAV 0 0 1 1 1 0 0E O/P I/O Port Bit 7
NSP 0 0 1 1 1 1 0F O/P
CRC Luma Error 0 1 0 0 0 0 10 O/P
CRC Chroma Error 0 1 0 0 0 1 11 O/P
F 0 1 0 0 1 0 12 O/P I/O Port Bit 0
V 0 1 0 0 1 1 13 O/P I/O Port Bit 1
H 0 1 0 1 0 0 14 O/P I/O Port Bit 2
Format[0] 0 1 0 1 0 1 15 O/P
Format[1] 0 1 0 1 1 0 16 O/P
Format[2] 0 1 0 1 1 1 17 O/P
Format[3] 0 1 1 0 0 0 18 O/P
Format[4] 0 1 1 0 0 1 19 O/P I/O Port Bit 3 (SD/HD)
FIFO Full 0 1 1 0 1 0 1A O/P
FIFO Empty 0 1 1 0 1 1 1B O/P I/O Port Bit 6
Lock Detect 0 1 1 1 0 0 1C O/P I/O Port Bit 4
Pass/Fail 0 1 1 1 0 1 1D O/P
FIFO Overrun 0 1 1 1 1 0 1E O/P
ANC Chksum Error 0 1 1 1 1 1 1F O/P
EDH Force 1 0 0 0 0 0 20 I/P
Test Pattern Select[0] 1 0 0 0 0 1 21 I/P
Test Pattern Select[1] 1 0 0 0 1 0 22 I/P
Test Pattern Select[2] 1 0 0 0 1 1 23 I/P
Test Pattern Select[3] 1 0 0 1 0 0 24 I/P
Test Pattern Select[4] 1 0 0 1 0 1 25 I/P
Test Pattern Select[5] 1 0 0 1 1 0 26 I/P
(1) Note: All LVCMOS inputs have internal pull-down devices except VCLK and ACLK.
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