Datasheet

ACLK
RD/WR
ANC/CTRL
AD[9:0]
READ
DATA DATA DATADATADATA DATA DATA
LMH0031
SNLS218A JANUARY 2006REVISED APRIL 2013
www.ti.com
Figure 5. Ancillary Data Read Timing
MULTI-FUNCTION I/O PORT
The multi-function I/O port can be configured to provide immediate access to many control and indicator
functions that are stored within the LMH0031’s configuration and control registers. The individual pins comprising
this port are assigned as input or output for selected functions stored in the control data registers.
The multi-function I/O port is configured by way of an 8x6-bit register bank consisting of registers I/O pin 0
CONFIG through I/O pin 7 CONFIG. The contents of these registers determine whether the port bits function as
inputs or outputs and to which control function or indicator each port bit is assigned. Port bits may be assigned to
access different functions and indicators or any or all port bits may be assigned to access the same function or
indicator (output mode only). The same indicator or function should not be assigned to more than one port bit as
an input. Controls and indicators that are accessible by the port and their corresponding selection addresses are
given in the I/O Pin Configuration Register Addresses, Table 6. Table 2 gives the control register bit
assignments.
Data resulting from device operation will be sent to the selected I/O port bit. This same data is also stored in the
configuration and control registers. Mapping the control and indicator functions in this manner means that device
operation will be immediately reflected at the I/O port pins thereby ensuring more reliable real-time operation of
the device within and by the host system.
When a multifunction I/O port bit is used as input to a control register bit, data must be presented to the I/O port
bit and clocked into the register bit using A
CLK
as shown in Figure 6. Port timing for bit write operations is the
same as for the ANC/CTRL port operation.
Figure 6. I/O Port Data Write Timing
Example: Program multi-function I/O port bit-0 as the CRC Luma Error bit output.
1. Set ANC/CTRL to a logic-low.
2. Set RD/WR to a logic-low.
3. Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG register address.
4. Toggle A
CLK
.
5. Present 310h to AD[9:0] as the register data.
6. Toggle A
CLK
.
16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH0031