Datasheet

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LMC662

www.ti.com

SNOSC51C –APRIL 1998–REVISED MARCH 2013

LMC662 CMOS Dual Operational Amplifier

Check for Samples: LMC662

FEATURES

DESCRIPTION

The LMC662 CMOS Dual operational amplifier is

• Rail-to-Rail Output Swing

ideal for operation from a single supply. It operates

• Specified for 2 kΩ and 600Ω Loads

from +5V to +15V and features rail-to-rail output

• High Voltage Gain: 126 dB

swing in addition to an input common-mode range

that includes ground. Performance limitations that

• Low Input Offset Voltage: 3 mV

have plagued CMOS amplifiers in the past are not a

• Low Offset Voltage Drift: 1.3 μV/°C

problem with this design. Input V

, drift, and

• Ultra Low Input Bias Current: 2 fA

broadband noise as well as voltage gain into realistic

loads (2 kΩ and 600Ω) are all equal to or better than

• Input Common-Mode Range Includes V

−

widely accepted bipolar equivalents.

• Operating Range from +5V to +15V Supply

This chip is built with TI's advanced Double-Poly

• I

= 400 μA/amplifier; Independent of V+

Silicon-Gate CMOS process.

• Low Distortion: 0.01% at 10 kHz

See the LMC660 datasheet for a Quad CMOS

• Slew Rate: 1.1 V/μs

operational amplifier with these same features.

APPLICATIONS

• High-Impedance Buffer or Preamplifier

• Precision Current-to-Voltage Converter

• Long-Term Integrator

• Sample-and-Hold Circuit

• Peak Detector

• Medical Instrumentation

• Industrial Controls

• Automotive Sensors

Connection Diagram

Typical Application

Figure 1. 8-Pin PDIP, SOIC

Figure 2. Low-Leakage Sample-and-Hold

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

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LMC662 www.ti.com SNOSC51C – APRIL 1998 – REVISED MARCH 2013 LMC662 CMOS Dual Operational Amplifier Check for Samples: LMC662 FEATURES DESCRIPTION • • • • • • • • • • • The LMC662 CMOS Dual operational amplifier is ideal for operation from a single supply. It operates from +5V to +15V and features rail-to-rail output swing in addition to an input common-mode range that includes ground. Performance limitations that have plagued CMOS amplifiers in the past are not a problem with this design.
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LMC662 SNOSC51C – APRIL 1998 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) (3) Differential Input Voltage ±Supply Voltage Supply Voltage (V+ − V−) 16V Output Short Circuit to V+ See (4) Output Short Circuit to V− See (5) Lead Temperature (Soldering, 10 sec.) 260°C Storage Temp. Range −65°C to +150°C (V+) +0.3V, (V−) −0.
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LMC662 www.ti.com SNOSC51C – APRIL 1998 – REVISED MARCH 2013 DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Parameter Test Conditions Input Offset Voltage Typ (1) LMC662AI LMC662C Limit (1) Limit (1) 1 Input Offset Voltage Average Drift 3 6 mV 3.3 6.3 max μV/°C 1.3 Input Bias Current 0.
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LMC662 SNOSC51C – APRIL 1998 – REVISED MARCH 2013 www.ti.com DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Parameter Output Current Test Conditions Sourcing, VO = 0V LMC662AI LMC662C Limit (1) Limit (1) 16 13 mA 14 11 min 16 13 mA 14 11 min 28 23 mA 25 21 min 39 28 23 mA 24 20 min 0.75 1.
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LMC662 www.ti.com SNOSC51C – APRIL 1998 – REVISED MARCH 2013 Typical Performance Characteristics VS = ±7.5V, TA = 25°C unless otherwise specified Supply Current vs. Supply Voltage Offset Voltage Figure 3. Figure 4. Input Bias Current Output Characteristics Current Sinking Figure 5. Figure 6. Output Characteristics Current Sourcing Input Voltage Noise vs. Frequency Figure 7. Figure 8.
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LMC662 SNOSC51C – APRIL 1998 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C unless otherwise specified CMRR vs. Frequency Open-Loop Frequency Response Figure 9. Figure 10. Frequency Response vs. Capacitive Load Non-Inverting Large Signal Pulse Response Figure 11. Figure 12. Stability vs. Capacitive Load Stability vs. Capacitive Load Note: Avoid resistive loads < 500Ω, as they may cause instability. Figure 13.
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LMC662 www.ti.com SNOSC51C – APRIL 1998 – REVISED MARCH 2013 APPLICATION HINTS AMPLIFIER TOPOLOGY The topology chosen for the LMC662, shown in Figure 15, is unconventional (compared to general-purpose op amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from the output of the integrator, to allow rail-to-rail output swing.
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LMC662 SNOSC51C – APRIL 1998 – REVISED MARCH 2013 www.ti.com However, if the feedback pole is less than approximately 6 to 10 times the “ideal” −3 dB frequency, a feedback capacitor, CF, should be connected between the output and the inverting input of the op amp.
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LMC662 www.ti.com SNOSC51C – APRIL 1998 – REVISED MARCH 2013 Using the smaller capacitors will give much higher bandwidth with little degradation of transient response.
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LMC662 SNOSC51C – APRIL 1998 – REVISED MARCH 2013 www.ti.com To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC662's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's inputs. See Figure 19. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board.
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LMC662 www.ti.com SNOSC51C – APRIL 1998 – REVISED MARCH 2013 Figure 22. Guard Ring Connections: Follower Figure 23. Guard Ring Connections: Howland Current Pump The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Do not insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator.
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LMC662 SNOSC51C – APRIL 1998 – REVISED MARCH 2013 www.ti.com BIAS CURRENT TESTING The test method of Figure 25 is appropriate for bench-testing bias current with reasonable accuracy. To understand its operation, first close switch S2 momentarily. When S2 is opened, then (10) Figure 25. Simple Input Bias Current Test Circuit A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric.
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LMC662 www.ti.com SNOSC51C – APRIL 1998 – REVISED MARCH 2013 (V+ = 5.0 VDC) Figure 27. Instrumentation Amplifier For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7. Oscillator frequency is determined by R1, R2, C1, and C2: fOSC = 1/2πRC where R = R1 = R2 and C = C1 = C2. Figure 28. Sine-Wave Oscillator This circuit, as shown, oscillates at 2.
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LMC662 SNOSC51C – APRIL 1998 – REVISED MARCH 2013 www.ti.com (V+ = 5.0 VDC) Figure 29. 1 Hz Square-Wave Oscillator Figure 30. Power Amplifier fO = 10 Hz Q = 2.1 Gain = −8.8 Figure 31.
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LMC662 www.ti.com SNOSC51C – APRIL 1998 – REVISED MARCH 2013 (V+ = 5.0 VDC) fc = 10 Hz d = 0.895 Gain = 1 2 dB passband ripple Figure 32. 10 Hz High-Pass Filter Figure 33. 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only) Gain = −46.8 Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV). Figure 34.
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LMC662 SNOSC51C – APRIL 1998 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision B (March 2013) to Revision C • 16 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC662AIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC662AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC662CMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC662AIMX SOIC D 8 2500 367.0 367.0 35.0 LMC662AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC662CMX SOIC D 8 2500 367.0 367.0 35.0 LMC662CMX/NOPB SOIC D 8 2500 367.0 367.0 35.
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