Datasheet

LMC6084
SNOS657D –AUGUST 2000–REVISED MARCH 2013 www.ti.com
Latchup
CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and
output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate
lead. The LMC6084 is designed to withstand 100 mA surge current on the I/O pins. Some resistive method
should be used to isolate any capacitance from supplying excess current to the I/O pins. In addition, like an SCR,
there is a minimum holding current for any latchup mode. Limiting current to the supply pins will also inhibit
latchup susceptibility.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board).
Figure 30. Air Wiring
Typical Single-Supply Applications
(V
+
= 5.0 V
DC
)
The extremely high input impedance, and low power consumption, of the LMC6084 make it ideal for applications
that require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held
pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure
transducers.
Figure 31 shows an instrumentation amplifier that features high differential and common mode input resistance
(>10
14
Ω), 0.01% gain accuracy at A
V
= 1000, excellent CMRR with 1 kΩ imbalance in bridge source resistance.
Input current is less than 100 fA and offset drift is less than 2.5 μV/°C. R
2
provides a simple means of adjusting
gain over a wide range without degrading CMRR. R
7
is an initial trim used to maximize CMRR without using
super precision matched resistors. For good CMRR over temperature, low drift resistors should be used.
If R
1
= R
5
, R
3
= R
6
, and R
4
= R
7
; then
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