Datasheet

LM96000
www.ti.com SNAS234C –APRIL 2004–REVISED MARCH 2013
The four least significant bits of the Version/Stepping register [3.0] contain the current stepping of the LM96000
silicon. The four most significant bits [7.4] reflect the LM96000 base device number when set to a value of
0110b. For the LM96000, this register will read 01101000b (68h). Bit 3 of the stepping field is set to indicate that
the LM96000 is a super-set of the LM85 family of products.
The register is used by application software to identify which device in the hardware monitor family of ASICs has
been implemented in the given system. Based on this information, software can determine which registers to
read from and write to. Further, application software may use the current stepping to implement work-arounds for
bugs found in a specific silicon stepping.
This register is read only — a write to this register has no effect.
4.7 Register 40h: Ready/Lock/Start/Override
Register Read/ Register Bit 7 Bit 0 Default
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Address Write Name (MSB) (LSB) Value
40h R/W Ready/Lo RES RES RES RES OVRID READY LOCK START 00h
ck/Start/O
verride
Bit Name R/W Default Description
0 START R/W 0 When software writes a 1 to this bit, the LM96000 fan monitoring and PWM output control
functions will use the values set in the fan control limit and parameter registers (address
5Ch through 6Eh). Before this bit is set, the LM96000 will not update the used register
values, the default values will remain in effect. Whenever this bit is set to 0, the LM96000
fan monitoring and PWM output control functions use the default fan limits and
parameters, regardless of the current values in the limit and parameter registers (5C
through 6Eh). The LM96000 will preserve the values currently stored in the limit and
parameter registers when this bit is set or cleared. This bit is not effected by the state of
the Lock bit.
It is expected that all limit and parameter registers will be set by BIOS or application
software prior to setting this bit.
1 LOCK R/W 0 Setting this bit to 1 locks specified limit and parameter registers. Once this bit is set, limit
and parameter registers become read only and will remain locked until the device is
powered off. This register bit becomes read only once it is set.
2 READY R 0 The LM96000 sets this bit automatically after the part is fully powered up, has completed
the power-up-reset process, and after all A/D converters are properly functioning.
3 OVRID R/W If this bit is set to 1, all PWM outputs will go to 100% duty cycle regardless of whether or
not the lock bit is set. The OVRID bit has precedence over the disabled mode. Therefore,
when OVRID is set the PWM will go to 100% even if the PWM is in the disabled mode.
4–7 Reserved R 0 Reserved
4.8 Register 41h: Interrupt Status Register 1
Register Read/ Register Bit 7 Bit 0 Default
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Address Write Name (MSB) (LSB) Value
41h R Interrupt ERR ZN3 ZN2 ZN1 5V 3.3V VCCP 2.5V 00h
Status 1
The Interrupt Status Register 1 bits will be automatically set, by the LM96000, whenever a fault condition is
detected. A fault condition is detected whenever a measured value is outside the window set by its limit registers.
ZN3 and ZN1 bits will be set when a diode fault condition, such as a disconect or short, is detected. More than
one fault may be indicated in the interrupt register when read. This register will hold a set bit(s) until the event is
read by software. The contents of this register will be cleared (set to 0) automatically by the LM96000 after it is
read by software, if the fault condition is no longer exists. Once set, the Interrupt Status Register 1 bits will
remain set until a read event occurs, even if the fault condition no longer exists
This register is read only — a write to this register has no effect.
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Product Folder Links: LM96000