Datasheet

+
-
+
-
10 PA
comp
ISENSE
amp
POWER
SUPPLY
100
100
100 pF
100 pF
LIMx
KSx
RSNSx
10 nF
20m
13k
LIMx
LM5642, LM5642X
SNVS219K –JUNE 2003–REVISED APRIL 2013 www.ti.com
Figure 29. Current Sense and Current Limit
Current limit is activated when the inductor current is high enough to cause the voltage at the RSNSx pin to be
lower than that of the ILIMx pin. This toggles the Ilim comparator, thus turning off the top FET immediately. The
comparator is disabled when the top FET is turned off and during the leading edge blanking time. The equation
for current limit resistor, R
lim
, is as follows:
where
• Ilim is the load current at which the current limit comparator will be tripped (4)
When sensing current across the top FET, replace Rsns with the R
DS-ON
of the FET. This calculated Rlim value
specifies that the minimum current limit will not be less than Imax. It is recommended that a 1% tolerance resistor
be used.
When sensing across the top FET (V
DS
sensing), R
DS-ON
will show more variation than a current-sense resistor,
largely due to temperature variation. R
DS-ON
will increase proportional to temperature according to a specific
temperature coefficient. Refer to the FET manufacturer's datasheet to determine the range of R
DS-ON
values over
operating temperature or see the Component Selection section (Equation 27) for a calculation of maximum R
DS-
ON
. This will prevent R
DS-ON
variations from prematurely tripping the current limit comparator as the operating
temperature increases.
To ensure accurate current sensing using V
DS
sensing, special attention in board layout is required. The KSx and
RSNSx pins require separate traces to form a Kelvin connection at the corresponding current sense nodes. In
addition, the filter components R14, R16, C14, C15 should be removed.
INPUT UNDER VOLTAGE LOCKOUT (UVLO)
The input under-voltage lock out threshold, which is sensed via the VLIN5 internal LDO output, is 4.0V (typical).
Below this threshold, both HDRVx and LDRVx will be turned off and the internal 480Ω MOSFETs will be turned
on to discharge the output capacitors through the SWx pins. When the input voltage is below the UVLO
threshold, the ON/SS pins will sink 5mA to discharge the soft start capacitors and turn off both channels. As the
input voltage increases again above 4.0V, UVLO will be de-activated, and the device will restart through a normal
soft start phase. If the voltage at VLIN5 remains below 4.5V, but above the 4.0V UVLO threshold, the device
cannot be ensured to operate within specification.
If the input voltage is between 4.0V and 5.2V, the VLIN5 pin will not regulate, but will follow approximately 200
mV below the input voltage.
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