Datasheet

LM5642, LM5642X
SNVS219K –JUNE 2003–REVISED APRIL 2013 www.ti.com
The equation for calculating the maximum total input ripple RMS current for duty cycles under 50% is:
where
• I1 is maximum load current of Channel 1
• I2 is the maximum load current of Channel 2
• D1 is the duty cycle of Channel 1
• D2 is the duty cycle of Channel 2 (21)
Example: Imax_1 = 3.6A, Imax_2 = 3.6A, D1 = 0.42, and D2 = 0.275
(22)
Choose input capacitors that can handle 1.66A ripple RMS current at highest ambient temperature. In
applications where output voltages are greater than half the input voltage, the corresponding duty cycles will be
greater than 50%, and there will be overlapping input current pulses. Input ripple current will be highest under
these circumstances. The input RMS current in this case is given by:
(23)
Where, again, I1 and I2 are the maximum load currents of channel 1 and 2, and D1 and D2 are the duty cycles.
This equation should be used when both duty cycles are expected to be higher than 50%.
If the LM5642 is being used with an external clock frequency other than 200kHz, or 375 kHz for the LM5642X,
the preceding equations for input rms current can still be used. The selection of the first equation or the second
changes because overlap can now occur at duty cycles that are less than 50%. From the EXTERNAL
FREQUENCY SYNC section, the maximum duty cycle that ensures no overlap between duty cycles (and hence
input current pulses) is:
D
MAX
= F
SYNC
*
2.5 x 10
-6
(24)
There are now three distinct possibilities which must be considered when selecting the equation for input rms
current. The following applies for the LM5642, and also the LM5642X by replacing 200 kHz with 375 kHz:
1. Both duty cycles D
1
and D
2
are less than D
MAX
. In this case, the first, simple equation can always be used.
2. One duty cycle is greater than D
MAX
and the other duty cycle is less than D
MAX
. In this case, the system
designer can take advantage of the fact that the sync feature reduces D
MAX
for one channel, but lengthens it
for the other channel. For F
SYNC
< 200kHz, D
1
is reduced to D
MAX
while D
2
actually increases to (1-D
MAX
).
For F
SYNC
> 200kHz, D
2
is reduced to D
MAX
while D
1
increases to (1-D
MAX
). By using the channel reduced to
D
MAX
for the lower duty cycle, and the channel that has been increased for the higher duty cycle, the first,
simple rms input current equation can be used.
3. Both duty cycles are greater than D
MAX
. This case is identical to a system at 200 kHz where either duty cycle
is 50% or greater. Some overlap of duty cycles is specified, and hence the second, more complicated rms
input current equation must be used.
Input capacitors must meet the minimum requirements of voltage and ripple current capacity. The size of the
capacitor should then be selected based on hold up time requirements. Bench testing for individual applications
is still the best way to determine a reliable input capacitor value. Input capacitors should always be placed as
close as possible to the current sense resistor or the drain of the top FET. When high ESR capacitors such as
tantalum are used, a 1µF ceramic capacitor should be added as closely as possible to the high-side FET drain
and low-side FET source.
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