Datasheet

LM5110
SNVS255A –MAY 2004–REVISED MAY 2004 www.ti.com
DETAILED OPERATING DESCRIPTION
LM5110 dual gate driver consists of two independent and identical driver channels with TTL compatible logic
inputs and high current totem-pole outputs that source or sink current to drive MOSFET gates. The driver output
consist of a compound structure with MOS and bipolar transistor operating in parallel to optimize current
capability over a wide output voltage and operating temperature range. The bipolar device provides high peak
current at the critical threshold region of the MOSFET VGS while the MOS devices provide rail-to-rail output
swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage V
CC
and the power
ground potential at the V
EE
pin.
The control inputs of the drivers are high impedance CMOS buffers with TTL compatible threshold voltages. The
negative supply of the input buffer is connected to the input ground pin IN_REF. An internal level shifting circuit
connects the logic input buffers to the totem pole output drivers. The level shift circuit and separate input/output
ground pins provide the option of single supply or split supply configurations. When driving MOSFET gates from
a single positive supply, the IN_REF and V
EE
pins are both connected to the power ground. The LM5110 pinout
was designed for compatibility with industry standard gate drivers in single supply gate driver applications. Pin 1
(IN_REF) on the LM5110 is a no-connect on standard driver IC's. Connecting pin 1 to pin 3 (V
EE
) on the printed
circuit board accommodates the pin-out of both the LM5110 and competitive drivers.
The isolated input/output grounds provide the capability to drive the MOSFET to a negative VGS voltage for a
more robust and reliable off state. In split supply configuration, the IN_REF pin is connected to the ground of the
controller which drives the LM5110 inputs. The V
EE
pin is connected to a negative bias supply that can range
from the IN-REF as much as 14V below the V
CC
gate drive supply. The maximum recommended voltage
difference between V
CC
and IN_REF or between V
CC
and V
EE
is 14V. The minimum voltage difference between
V
CC
and IN_REF is 3.5V.
Enhancement mode MOSFETs do not inherently require a negative bias on the gate to turn off the FET.
However, certain applications may benefit from the capability of negative VGS voltage during turn-off including:
1. when the gate voltages cannot be held safely below the threshold voltage due to transients or coupling in the
printed circuit board.
2. when driving low threshold MOSFETs at high junction temperatures
3. when high switching speeds produce capacitive gate-drain current that lifts the internal gate potential of the
MOSFET
The two driver channels of the LM5110 are designed as identical cells. Transistor matching inherent to integrated
circuit manufacturing ensures that the ac and dc performance of the channels are nearly identical. Closely
matched propagation delays allow the dual driver to be operated as a single driver if inputs and output pins are
connected. The drive current capability in parallel operation is 2X the drive of either channel. Small differences in
switching speed between the driver channels will produce a transient current (shoot-through) in the output stage
when two output pins are connected to drive a single load. The efficiency loss for parallel operation has been
characterized at various loads, supply voltages and operating frequencies. The power dissipation in the LM5110
increases by less than 1% relative to the dual driver configuration when operated as a single driver with inputs
and outputs connected.
An Under-voltage lockout (UVLO) circuit is included in the LM5110, which senses the voltage difference between
V
CC
and the input ground pin, IN_REF. When the V
CC
to IN_REF voltage difference falls below 2.7V both driver
channels are disabled. The driver will resume normal operation when the V
CC
to IN_REF differential voltage
exceeds approximately 2.9V. UVLO hysteresis prevents chattering during brown-out conditions.
The Shutdown pin (nSHDN) is a TTL compatible logic input provided to enable/disable both driver channels.
When nSHDN is in the logic low state, the LM5110 is switched to a low power standby mode with total supply
current less than 25 µA. This function can be effectively used for start-up, thermal overload, or short circuit fault
protection. It is recommended that this pin be connected to V
CC
when the shutdown function is not being used.
The shutdown pin has an internal 18μA current source pull-up to V
CC
.
The input pins of non-inverting drivers have an internal 18μA current source pull-down to IN-REF. The input pins
of inverting driver channels have neither pull-up nor pull-down current sources.
The LM5110 is available in dual non-inverting (-1), dual inverting (-2) and the combination inverting plus non-
inverting (-3) configurations. All three configurations are offered in the SOIC-8 and WSON-10 plastic packages.
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