Datasheet
LM5085, LM5085-Q1
SNVS565G –NOVEMBER 2008–REVISED MARCH 2013
www.ti.com
Electrical Characteristics (continued)
Limits in standard type are for T
J
= 25°C only; limits in boldface type apply over the junction temperature (T
J
) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at T
J
= 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 48V, R
T
= 100kΩ.
Symbol Parameter Conditions Min Typ Max Units
V
CL OFFSET
Current Limit Comparator Offset V
ADJ
= 46.5V, V
ADJ
- V
ISEN
-9 0 9 mV
RT Pin
RT
SD
Shutdown Threshold RT Pin Voltage Rising 0.73 V
RT
HYS
Shutdown Threshold Hysteresis 50 mV
On-Time
t
ON – 1
On-Time VIN = 4.5V, R
T
= 100kΩ 3.5 5 7.15 µs
t
ON – 2
VIN = 48V, R
T
= 100kΩ 276 360 435 ns
t
ON - 3
VIN = 75V, R
T
= 100kΩ 177 235 285 ns
t
ON - 4
Minimum On-Time in Current Limit
(3)
VIN = 48V, 25mV Overdrive at ISEN 55 140 235 ns
Off-Time
t
OFF(CL1)
VIN = 12V, V
FB
= 0V 5.35 7.9 10.84 µs
t
OFF(CL2)
VIN = 12V, V
FB
= 1V 1.42 1.9 3.03 µs
Off-Time (Current Limit)
(3)
t
OFF(CL3)
VIN = 48V, V
FB
= 0V 16 24 32.4 µs
t
OFF(CL4)
VIN = 48V, V
FB
= 1V 3.89 5.7 8.67 µs
Regulation and Over-Voltage Comparators (FB Pin)
V
REF
FB Regulation Threshold 1.225 1.25 1.275 V
V
OV
FB Over-Voltage Threshold Measured with Respect to V
REF
350 mV
I
FB
FB Bias Current 10 nA
Soft-Start Function
t
SS
Soft-Start Time 1.4 2.5 4.3 ms
Thermal Shutdown
T
SD
Junction Shutdown Temperature Junction Temperature Rising 170 °C
T
HYS
Junction Shutdown Hysteresis 20 °C
Thermal Resistance
(4)
θ
JA
Junction to Ambient, 0 LFPM Air Flow
(5)
VSSOP-8 Package 126 °C/W
HVSSOP-8 Package 46
WSON-8 Package 54
θ
JC
Junction to Case, 0 LFPM Air Flow
(5)
VSSOP-8 Package 29 °C/W
HVSSOP-8 Package 5.5
WSON-8 Package 9.1
(3) The tolerance of the minimum on-time (t
ON
-4) and the current limit off-times (t
OFF(CL1)
through (t
OFF(CL4)
) track each other over process
and temperature variations. A device which has an on-time at the high end of the range will have an off-time that is at the high end of its
range.
(4) For detailed information on soldering plastic VSSOP and WSON packages visit www.ti.com/packaging.
(5) Tested on a 4 layer JEDEC board. Four vias provided under the exposed pad. See JEDEC standards JESD51-5 and JESD51-7.
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