Datasheet

RT =
1
F x 330 x 10
-12
RT =
1
F x 165 x 10
-12
LM5071
www.ti.com SNVS409E –NOVEMBER 2005–REVISED APRIL 2013
Oscillator, Shutdown and Sync Capability
A single external resistor connected between the RT and ARTN pins sets the LM5071 oscillator frequency.
Internal to the LM5071–50 device (50% duty cycle limited option) is an oscillator divide by two circuit. This divide
by two circuit creates an exact 50% duty cycle clock which is used internally to create a precise 50% duty cycle
limit function. Because of this divide by two, the internal oscillator actually operates at twice the frequency of the
output (OUT). For the LM5071–80 device the oscillator frequency and the operational output frequency are the
same. To set a desired output operational frequency (F), the RT resistor can be calculated from:
LM5071-80:
(1)
LM5071-50:
(2)
The LM5071 can also be synchronized to an external clock. The external clock must have a higher frequency
than the free running oscillator frequency set by the RT resistor. The clock signal should be capacitively coupled
into the RT pin with a 100pF capacitor. A peak voltage level greater than 3.7 volts at the RT pin is required for
detection of the sync pulse. The sync pulse width should be set between 15 to 150ns by the external
components. The RT resistor is always required, whether the oscillator is free running or externally synchronized.
The voltage at the RT pin is internally regulated to a 2 volts. The RT resistor should be located very close to the
device and connected directly to the pins of the controller (RT and ARTN).
PWM Comparator / Slope Compensation
The PWM comparator compares the current ramp signal with the loop error voltage derived from the error
amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4V and then further attenuated
by a 3:1 resistor divider. The PWM comparator polarity is such that 0 Volts on the COMP pin will result in zero
duty cycle at the controller output. For duty cycles greater than 50 percent, current mode control circuits are
subject to sub-harmonic oscillation. By adding an additional fixed slope voltage ramp signal (slope compensation)
to the current sense signal, this oscillation can be avoided. The LM5071-80 integrates this slope compensation
by summing a current ramp generated by the oscillator with the current sense signal. Additional slope
compensation may be added by increasing the source impedance of the current sense signal (with an external
resistor between the CS pin and current sense resistor). Since the LM5071-50 is not capable of duty cycles
greater than 50%, there is no slope compensation feature in this device.
Soft-Start
The softstart feature allows the power converter to gradually reach the initial steady state operating point, thereby
reducing start-up stresses, output overshoot and current surges. At power on, after the V
CC
undervoltage lockout
threshold is satisfied, an internal 10μA current source charges an external capacitor connected to the SS pin.
The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output
pulses.
Gate Driver and Maximum Duty Cycle Limit
The LM5071 provides an internal gate driver (OUT), which can source and sink a peak current of 800mA. The
LM5071 is available in two duty cycle limit options. The maximum output duty cycle is typically 80% for the
LM5071-80 option and precisely equal to 50% for the LM5071-50 option. The maximum duty cycle function for
the LM5071-50 is accomplished with an internal toggle flip-flop which ensures an accurate duty cycle limit. The
internal oscillator frequency of the LM5071-50 is therefore twice the operating frequency of the PWM controller
(OUT pin).
The 80% maximum duty cycle limit of the LM5071-80 is determined by the internal oscillator and varies more
than the 50% limit of the LM5071-50. For the LM5071-80, the internal oscillator frequency and the operational
frequency of the PWM controller are equal.
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