Datasheet

LM5070
www.ti.com SNVS308G –OCTOBER 2004–REVISED APRIL 2013
Classification
To classify the PD, the PSE will present a voltage between 14.5V and 20.5V to the PD. The LM5070 enables
classification mode at a nominal input voltage of 11.5V. An internal 1.5V linear regulator and an external resistor
connected to the RCLASS pin provide classification programming current. Table 2 shows the external
classification resistor required for a particular class.
The classification current flows through the IC into the classification resistor. The suggested resistor values take
into account the bias current flowing into the IC. A different desired RCLASS can be calculated by dividing 1.5V
by the desired classification current.
Per the IEEE 802.3af specification, classification is optional, and the PSE will default to class 0 if a valid
classification current is not detected. If PD classification is not desired (i.e., Class 0), simply leave the RCLASS
pin open. The classification time period may not last longer then 75ms as per IEEE 802.3af. The LM5070 will
remain in classification mode until V
IN
is greater than 22V.
Table 2. Classification Levels and Required External Resistors
Class PMIN PMAX ICLASS ICLASS RCLASS
(MIN) (MAX)
0 0.44W 12.95W 0mA 4mA Open
1 0.44W 3.84W 9mA 12mA 150Ω
2 3.84W 6.49W 17mA 20mA 82.5Ω
3 6.49W 12.95W 26mA 30mA 53.6Ω
4 Reserved Reserved 36mA 44mA 38.3Ω
Undervoltage Lockout (UVLO)
The IEEE 802.3af specification states that the PSE will supply power to the PD within 400ms after completion of
detection. The LM5070 contains a programmable line Under Voltage Lock Out (UVLO) circuit. The first resistor
should be connected between the V
IN
to UVLO pins; the bottom resistor in the divider should be connected
between the UVLO and UVLORTN pins. The bottom resistor should not be tied to V
EE
because any current from
V
IN
to V
EE
will cause the system to violate the 10uA maximum offset current specification during detection mode.
The divider must be designed such that the voltage at the UVLO pin equals 2.0V when V
IN
reaches the desired
minimum operating level. If the UVLO threshold is not met, the interface control and SMPS control will remain in
standby.
UVLO hysteresis is accomplished with an internal 10uA current source that is switched on and off into the
impedance of the UVLO set point divider. When the UVLO threshold is exceeded, the current source is activated
to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.00V threshold, the
current source is turned off, causing the voltage at the UVLO pin to fall. The LM5070 UVLO thresholds cannot be
programmed lower than 23V, otherwise the device would operate in classification mode with both the
classification current source and the SMPS enabled. The combined power dissipation of these two functions
could exceed the maximum power dissipation of the package.
There are many additional uses for the UVLO pin. The UVLO function can also be used to implement a remote
enable / disable function. Pulling the UVLO pin down below the UVLO threshold disables the interface and SMPS
controller.
Power Supply Operation / Current Limit Programming
Once the UVLO threshold has been satisfied, the interface controller of the LM5070 will charge up the SMPS
input capacitor through the internal power MOSFET. This load capacitance provides input filtering for the power
converter section and must be at least 5uF per the IEEE 802.3af specification. To accomplish the charging in a
controlled manner, the power MOSFET is current limited to 375mA. The IEEE 802.3af specification requires that
the load capacitance be charged within 75ms.
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