Datasheet

OUT1
OUT2
AC2
AC1
1/Fs
Main Switch On
Active Clamp Switch On
t
OVLP
t
OVLP
t
OVLP
t
OVLP
PWM
OUT
GND
LM503
4
V
CC
LM5034
SNVS347A –FEBRUARY 2005–REVISED APRIL 2013 www.ti.com
OUT1 and OUT2 are compound gate drivers with CMOS and Bipolar output transistors as shown in Figure 24.
The parallel MOS and Bipolar devices provide a faster turn-off of the primary switch thereby reducing switching
losses. The outputs switch at one-half the oscillator frequency with the rising edges at OUT1 and OUT2 180° out
of phase with each other. The on-time of OUT1 and OUT2 is determined by their respective duty cycle control.
The active clamp outputs are in phase with their respective main outputs, with their edge timing altered by the
overlap control circuit as shown in Figure 25. The overlap time provides deadtime between the operation of the
primary switch and the active clamp switch at both the rising and falling edges. The overlap times are the same
at the rising and falling edges, independent of frequency and duty cycle. The overlap time is programmed by the
resistor at the OVLP pin (R
OVLP
) according to the following equation (see Figure 15 and Figure 17):
t
OVLP
= (1.25 x R
OVLP
) + 5 (3)
where R
OVLP
is in kΩ, and t
OVLP
is in ns. The range for R
OVLP
is 10 kΩ to 100 kΩ. If the application requires zero
overlap time, the OVLP pin should be left open.
Figure 24. Compound Gate Driver
Figure 25. Output Overlap Timing
Thermal Shutdown
The LM5034 should be operated so the junction temperature does not exceed 125°C. If a junction temperature
transient reaches 165°C (typical), the Thermal Shutdown circuit activates the V
CC
Disable and Drivers Off lines
(see Figure 20). The V
CC
regulator and the four output drivers are disabled, the SS1, SS2, and RES pins are
grounded, and the soft-start current is set to 50 µA. This puts the LM5034 in a low power state helping to prevent
catastrophic failures from accidental device overheating. When the junction temperature reduces below 145°C
(typical hysteresis = 20°C), the V
CC
regulator is enabled and a startup sequence is initiated (Figure 5).
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