Datasheet

P
CIN
=
I
IN-RMS
2
x ESR
n
LM5022
www.ti.com SNVS480G –JANUARY 2007–REVISED DECEMBER 2013
INPUT CAPACITOR LOSS
This term represents the loss as input ripple current passes through the ESR of the input capacitor bank. In this
equation ‘n’ is the number of capacitors in parallel. The 4.7 µF input capacitors selected have a combined ESR
of approximately 1.5 mΩ, and Δi
L
for a 13.8V input is 0.55A:
(59)
I
IN-RMS
= 0.29 x Δi
L
= 0.29 x 0.55 = 0.16A P
CIN
= [0.16
2
x 0.0015] / 2 = 0.02 mW (negligible) (60)
OUTPUT CAPACITOR LOSS
This term is calculated using the same method as the input capacitor loss, substituting the output capacitor RMS
current for V
IN
= 13.8V. The output capacitors' combined ESR is also approximately 1.5 mΩ.
I
O-RMS
= 1.13 x 1.5 x (0.66 x 0.34)
0.5
= 0.8A P
CO
= [0.8 x 0.0015] / 2 = 0.6 mW (61)
BOOST INDUCTOR LOSS
The typical DCR of the selected inductor is 40 mΩ.
P
DCR
= I
L
2
x DCR P
DCR
= 1.5
2
x 0.04 = 90 mW (62)
Core loss in the inductor is estimated to be equal to the DCR loss, adding an additional 90 mW to the total
inductor loss.
TOTAL LOSS
P
LOSS
= Sum of All Loss Terms = 972 mW (63)
EFFICIENCY
η = 20 / (20 + 0.972) = 95% (64)
Layout Considerations
To produce an optimal power solution with the LM5022, good layout and design of the PCB are as important as
the component selection. The following are several guidelines to aid in creating a good layout.
FILTER CAPACITORS
The low-value ceramic filter capacitors are most effective when the inductance of the current loops that they filter
is minimized. Place C
INX
as close as possible to the VIN and GND pins of the LM5022. Place C
OX
close to the
load, and C
F
next to the VCC and GND pins of the LM5022.
SENSE LINES
The top of R
SNS
should be connected to the CS pin with a separate trace made as short as possible. Route this
trace away from the inductor and the switch node (where D1, Q1, and L1 connect). For the voltage loop, keep
R
FB1/2
close to the LM5022 and run a trace from as close as possible to the positive side of C
OX
to R
FB2
. As with
the CS line, the FB line should be routed away from the inductor and the switch node. These measures minimize
the length of high impedance lines and reduce noise pickup.
COMPACT LAYOUT
Parasitic inductance can be reduced by keeping the power path components close together and keeping the
area of the loops that high currents travel small. Short, thick traces or copper pours (shapes) are best. In
particular, the switch node should be just large enough to connect all the components together without excessive
heating from the current it carries. The LM5022 (boost converter) operates in two distinct cycles whose high
current paths are shown in Figure 25:
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