Datasheet

I
PK
=
R
CL
1.5A x (150 m: + R
CL
)
+ I
OR(MAX)
R
CL
=
1.0A x 0.11:
I
PK-
- 1.0A
I
PK-
= I
O(max)
-
2
I
OR(min)
LM5010A
LM5010A-Q1
www.ti.com SNVS376E –OCTOBER 2005–REVISED FEBRUARY 2013
(24)
where I
O(max)
is the maximum load current, and I
OR(min)
is the minimum ripple current calculated using
Equation 20. R
CL
is calculated from:
(25)
where 0.11Ω is the minimum value of the internal resistance from SGND to ISEN. The next smaller standard
value resistor should be used for R
CL
. With the addition of R
CL
, and when the circuit is in current limit, the upper
peak current out of the SW pin (I
PK
in Figure 10) can be as high as:
(26)
where I
OR(max)
is calculated using Equation 14. The inductor L1 and diode D1 must be rated for this current. If I
PK
exceeds 2A , the inductor value must be increased to reduce the ripple amplitude. This will necessitate
recalculation of I
OR(min)
, I
PK-
, and R
CL
.
Increasing the circuit’s current limit will increase power dissipation and the junction temperature within the
LM5010A. See PC BOARD LAYOUT AND THERMAL CONSIDERATIONS for guidelines on this issue.
PC BOARD LAYOUT AND THERMAL CONSIDERATIONS
The LM5010A regulation, over-voltage, and current limit comparators are very fast, and will respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be
as neat and compact as possible, and all the components must be as close as possible to their associated pins.
The two major current loops have currents which switch very fast, and so the loops should be as small as
possible to minimize conducted and radiated EMI. The first loop is that formed by C1, through the VIN to SW
pins, L1, C2, and back to C1. The second loop is that formed by D1, L1, C2, and the SGND and ISEN pins. The
ground connection from C2 to C1 should be as short and direct as possible, preferably without going through
vias. Directly connect the SGND and RTN pin to each other, and they should be connected as directly as
possible to the C1/C2 ground line without going through vias. The power dissipation within the IC can be
approximated by determining the total conversion loss (P
IN
- P
OUT
), and then subtracting the power losses in the
free-wheeling diode and the inductor. The power loss in the diode is approximately:
P
D1
= I
O
x V
F
x (1-D) (27)
where I
O
is the load current, V
F
is the diode’s forward voltage drop, and D is the duty cycle. The power loss in the
inductor is approximately:
P
L1
= I
O
2
x R
L
x 1.1 (28)
where R
L
is the inductor’s DC resistance, and the 1.1 factor is an approximation for the AC losses. If it is
expected that the internal dissipation of the LM5010A will produce high junction temperatures during normal
operation, good use of the PC board’s ground plane can help considerably to dissipate heat. The exposed pad
on the IC package bottom should be soldered to a ground plane, and that plane should both extend from
beneath the IC, and be connected to exposed ground plane on the board’s other side using as many vias as
possible. The exposed pad is internally connected to the IC substrate. The use of wide PC board traces at the
pins, where possible, can help conduct heat away from the IC. The four No Connect pins on the HTSSOP
package are not electrically connected to any part of the IC, and may be connected to ground plane to help
dissipate heat from the package. Judicious positioning of the PC board within the end product, along with the use
of any available air flow (forced or natural convection) can help reduce the junction temperature.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM5010A LM5010A-Q1