Datasheet

LM49450
SNAS440D –FEBRUARY 2008–REVISED MAY 2013 www.ti.com
Low Power Shutdown
The LM49450 features an I
2
C selectable low power shutdown mode that disables the entire device, reducing
quiescent current consumption to 0.05µA (digital + analog current). Set bit B0 in the mode control register
(0x00h) to 0 to disable the device. Set B0 to 1 to enable the device.
I
2
S CLOCK CONTROL
The LM49450 features the ability to derive multiple clock signals, including the DAC clock, I
2
S clock and word
select clock in master mode, and the charge pump oscillator frequency, from the MCLK input.
DAC Clock Divider (RDIV)
Bits B5-B0 in the CLOCK CONTROL register (0x01h) are the RDIV bits that set the DAC clock divider ratio. The
DAC clock derived from MCLK needs to match the DAC sampling rate. For example, with f
MCLK
= 12.288MHz
and a 64*f
S
oversampling ratio (f
S
= 48kHz), the DAC requires a 6.144MHz clock. In this case, set the RDIV ratio
to divide by 2. In other instances, there may not be a suitable divider ratio for a given sampling rate and MCLK
frequency. In this case, f
MCLK
may need to be altered. See the Clock Control Register section for more
information.
I
2
S WS Clock Dividers (I
2
S_CLK, WS_CLK)
In I
2
S master mode, the LM49450 I
2
S CLOCK CONTROL register (0x04h) can be used to set the I
2
S clock and
WS clock frequency. In I
2
S clock master mode, bits B7-B4 of the I
2
S CLOCK CONTROL register, the I
2
S_CLK
bits, set the I
2
S clock divider ratio. The LM49450 derives the I
2
S clock from DAC clock based on the ratio set by
the I
2
S_CLK bits. The I
2
S clock is output on I
2
S_CLK.
In I
2
S master mode, bits B3 and B2 (I
2
S_WS) of the I
2
S CLOCK CONTROL register set the bit length per data
word of the I
2
S WS.
Charge Pump Clock Divider (CPDIV)
The ground referenced headphone amplifiers charge pump derives its clock from MCLK. Bits B7-B0 of the
CHARGE PUMP CLOCK register (0x02h) set the charge pump clock divider ratio. See the Charge Pump Clock
Register section for more information.
Table 1. CONTROL REGISTERS — Register Map
Register Register B7 B6 B5 B4 B3 B2 B1 B0
Addess Name
MODE DAC_MO DAC_MODE
0x00h EXT_REF COMP SS MUTE LINE_IN ENABLE
CONTROL DE_1 _ 0
DAC_DIT DAC_DIT
0x01h CLOCK RDIV_5 RDIV_4 RDIV_3 RDIV_2 RDIV_1 RDIV_0
HER_OFF HER_ON
CHARGE PUMP
0x02h CLOCK CPDIV_7 CPDIV_6 CPDIV_5 CPDIV_4 CPDIV_3 CPDIV_2 CPDIV_1 CPDIV_0
FREQUENCY
I2S I
2
S_WOR
RESERVE I2S_WRD I2S_WRD_ I
2
S_MODE_ I
2
S_MODE
0x03h I2S MODE I2S_WRD_1 STEREO D
D _2 0 1_ _0
_REVERSE _ORDER
0x04h I
2
S CLOCK I2S_CLK_ I2S_CLK_ I2S_CLK_1 I2S_CLK_0 I2S_WS_1 I2S_WS_0 I2S_WS_M I2S_CLK_
3 2 S MS
HEADPHONE 3D RESERVE HP_3DAT HP_3DFREQ HP_3DFRE HP_3D_GAI HP_3D_G HP_3D_MO
0x05h HP_3DEN
CONTROL D TN _1 Q_0 N_1 AIN_0 DE
0x06h SPEAKER 3D RESERVE LS_3DAT LS_3DFREQ LS_3DFRE LS_3DGAIN LS_3DGAI LS_3D_MO LS_3DEN
CONTROL D TN _1 Q_0 _1 N_0 DE
HEADPHONE
RESERVE RESERVE
0x07h VOLUME RESERVED HP4 HP3 HP2 HP1 HP0
D D
CONTROL
SPEAKER
RESERVE RESERVE
0x08h VOLUME RESERVED LS4 LS3 LS2 LS1 LS0
D D
CONTROL
0x09h CMP_0_LSB C0_7 C0_6 C0_5 C0_4 C0_3 C0_2 C0_1 C0_0
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