Datasheet

SDA
SCL
1
8
2
3
7
6
5
8
10
4 9
1 7
ack from slave
ack from slave
w rs r stop
ack from slave ack from masterrepeated start data from slave
start
w ack ack rs
r ack ack stop
start
SCL
SDA
MSB Chip Address LSB
slave address =
0011010
2
register address = 0x00h
MSB Register 0x00h LSB
MSB Data LSB
MSB Chip Address LSB
slave address =
0011010
2
register 0x00h data
ack ack ack ack
start
MSB Chip Address LSB w
ack
MSB Register 0x02h LSB
ack
MSB Data LSB
ack
stop
ack from slave
ack from slave ack from slave
SCL
SDA
start
slave address =
0011010
2
w ack
register address = 0x02h
ack ack
register 0x02h data
stop
ADR6
Bit7
ADR5
bit6
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
R/W
bit0
MSB LSB
I
2
C SLAVE address (chip address)
LM49350, LM49350RLEVAL
www.ti.com SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012
Figure 50. I
2
C Chip Address
Register changes take effect at the SCL rising edge during the last ACK from slave.
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
Figure 51. Example I
2
C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the Figure 52 waveform.
Figure 52. Example I
2
C Read Cycle
Figure 53. I
2
C Timing Diagram
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