Datasheet

K =
P
OUT
P
OUT
+ P
LOSS
K =
P
OUT
P
IN
x R2
R1 =
V
REF
V
OUT
- 1
LM2832
SNVS455A –AUGUST 2006–REVISED APRIL 2013 www.ti.com
When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the
output ripple will be approximately sinusoidal and 90° phase shifted from the switching action. Given the
availability and quality of MLCCs and the expected output voltage of designs using the LM2832, there is really no
need to review any other capacitor technologies. Another benefit of ceramic capacitors is their ability to bypass
high frequency noise. A certain amount of switching edge noise will couple through parasitic capacitances in the
inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not. Since the output
capacitor is one of the two external components that control the stability of the regulator control loop, most
applications will require a minimum of 22 µF of output capacitance. Capacitance often, but not always, can be
increased significantly with little detriment to the regulator stability. Like the input capacitor, recommended
multilayer ceramic capacitors are X7R or X5R types.
CATCH DIODE
The catch diode (D1) conducts during the switch off-time. A Schottky diode is recommended for its fast switching
times and low forward voltage drop. The catch diode should be chosen so that its current rating is greater than:
I
D1
= I
OUT
x (1-D) (12)
The reverse breakdown rating of the diode must be at least the maximum input voltage plus appropriate margin.
To improve efficiency, choose a Schottky diode with a low forward voltage drop.
OUTPUT VOLTAGE
The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and
R1 is connected between V
O
and the FB pin. A good value for R2 is 10kΩ. When designing a unity gain
converter (Vo = 0.6V), R1 should be between 0Ω and 100Ω, and R2 should be equal or greater than 10kΩ.
(13)
V
REF
= 0.60V (14)
PCB LAYOUT CONSIDERATIONS
When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The
most important consideration is the close coupling of the GND connections of the input capacitor and the catch
diode D1. These ground ends should be close to one another and be connected to the GND plane with at least
two through-holes. Place these components as close to the IC as possible. Next in importance is the location of
the GND connection of the output capacitor, which should be near the GND connections of CIN and D1. There
should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node
island. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise
pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with
the GND of R1 placed as close as possible to the GND of the IC. The V
OUT
trace to R2 should be routed away
from the inductor and any other traces that are switching. High AC currents flow through the V
IN
, SW and V
OUT
traces, so they should be as short and wide as possible. However, making the traces wide increases radiated
noise, so the designer must make this trade-off. Radiated noise can be decreased by choosing a shielded
inductor. The remaining components should also be placed as close as possible to the IC. Please see
Application Note AN-1229 SNVA054 for further considerations and the LM2832 demo board as an example of a
four-layer layout.
Calculating Efficiency, and Junction Temperature
The complete LM2832 DC/DC converter efficiency can be calculated in the following manner.
(15)
Or
(16)
Calculations for determining the most significant power losses are shown below. Other losses totaling less than
2% are not discussed.
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