Datasheet

1
2
3
6
5
4
BOOST
GND
FB
SW
V
IN
EN
DAP
5
4
6
3
2
1
BOOST
GND
FB
EN
V
IN
SW
LM2734
V
IN
V
IN
EN
BOOST
SW
FB
GND
V
OUT
C3
L1
C1
C2
R1
R2
D1
D2
ON
OFF
LM2734Z
SNVS334E –JANUARY 2005–REVISED APRIL 2013 www.ti.com
Typical Application Circuit
Efficiency vs Load Current
V
IN
= 5V, V
OUT
= 3.3V
Connection Diagrams
Figure 1. 6-Lead SOT Figure 2. 6-Lead WSON (3mm x 3mm)
See Package Number DDC (R-PDSO-G6) See Package Number NGG0006A
PIN DESCRIPTIONS
Pin Name Function
1 BOOST Boost voltage that drives the internal NMOS control switch. A bootstrap
capacitor is connected between the BOOST and SW pins.
2 GND Signal and Power ground pin. Place the bottom resistor of the feedback
network as close as possible to this pin for accurate regulation.
3 FB Feedback pin. Connect FB to the external resistor divider to set output
voltage.
4 EN Enable control input. Logic high enables operation. Do not allow this pin to
float or be greater than V
IN
+ 0.3V.
5 V
IN
Input supply voltage. Connect a bypass capacitor to this pin.
6 SW Output switch. Connects to the inductor, catch diode, and bootstrap
capacitor.
DAP GND The Die Attach Pad is internally connected to GND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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