Datasheet

LM2642
www.ti.com SNVS203I –MAY 2002–REVISED APRIL 2013
(2)
Where Ilim is the load current at which the current limit comparator will be tripped.
When sensing current across the top FET, replace Rsns with the Rdson of the FET. This calculated Rlim value
specifies that the minimum current limit will not be less than Imax. It is recommended that a 1% tolerance resistor
be used.
When sensing across the top FET, Rdson will show more variation than a current sense resistor, largely due to
temperature. Rdson will increase proportional to temperature according to a specific temperature coefficient.
Refer to the manufacturer's datasheet to determine the range of Rdson values over operating temperature or see
the Component Selection section (equation 12) for a calculation of maximum Rdson. This will prevent Rdson
variations from prematurely setting off the current limit comparator as the operating temperature increases.
To ensure accurate current sensing, special attention in board layout is required. The KSx and RSNSx pins
require separate traces to form a Kelvin connection to the corresponding current sense nodes.
INPUT UNDER VOLTAGE LOCKOUT (UVLO)
The input under-voltage lock out threshold, which is sensed via the VLIN5 internal LDO output, is 4.0V (typical).
Below this threshold, both HDRVx and LDRVx will be turned off and the internal 480Ω MOSFETs will be turned
on to discharge the output capacitors through the SWx pins. During UVLO, the ON/SS pins will sink 5mA to
discharge the soft start capacitors and turn off both channels. As the input voltage increases again above 4.0V,
UVLO will be de-activated, and the device will restart again from soft start phase. If the voltage at VLIN5 remains
below 4.5V, but above the 4.0V UVLO threshold, the device cannot be ensured to operate within specification.
If the input voltage is between 4.0V and 5.2V, the VLIN5 pin will not regulate, but will follow approximately
200mV below the input voltage.
DUAL-PHASE PARALLEL OPERATION
In applications with high output current demand, the two switching channels can be configured to operate as a
two-180° out of phase converter to provide a single output voltage with current sharing between the two
switching channels. This approach greatly reduces the stress and heat on the output stage components while
lowering input ripple current. The sum of inductor ripple current is also reduced which results in lowering output
ripple voltage. Figure 3 shows an example of a typical two-phase circuit. Because precision current sense is the
primary design criteria to ensure accurate current sharing between the two channels, both channels must use
external sense resistors for current sensing. To minimize the error between the error amplifiers of the two
channels, tie the feedback pins FB1 and FB2 together and connect to a single voltage divider for output voltage
sensing. Also, tie the COMP1 and COMP2 together and connect to the compensation network. ON/SS1 and
ON/SS2 must be tied together to enable and disable both channels simultaneously.
COMPONENT SELECTION
OUTPUT VOLTAGE SETTING
The output voltage for each channel is set by the ratio of a voltage divider as shown in Figure 27. The resistor
values can be determined by the following equation:
(3)
Where Vfb=1.238V. Although increasing the value of R1 and R2 will increase efficiency, this will also decrease
accuracy. Therefore, a maximum value is recommended for R2 in order to keep the output within .3% of Vnom.
This maximum R2 value should be calculated first with the following equation:
(4)
Where 200nA is the maximum current drawn by FBx pin.
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