Datasheet

TIMER
Pin
Load
Current
Output
Voltage
(OUT Pin)
PGD
UVLO
Normal Operation
GATE
Pin
Insertion Time
POR
V
SYS
V
IN
I
LIMIT
20 PA source
2.5 PA
80
PA
t 3
t 2t 1
In-rush
Limiting
5.5
PA
1.72V
2 mA
2 mA pull-down
260 mA
pull-down
FB Threshold
LM25061
SNVS611E –FEBRUARY 2011–REVISED MARCH 2013 www.ti.com
Figure 23. Power Up Sequence (Current Limit only)
Gate Control
A charge pump provides the voltage at the GATE pin to enhance the N-Channel MOSFET’s gate. During normal
operating conditions (t3 in Figure 23) the gate of Q1 is held charged by an internal 20 µA current source. The
voltage at the GATE pin (with respect to ground) is limited by an internal 19.5V zener diode. See the graph “
GATE Pin Voltage”. Since the gate-to-source voltage applied to Q1 could be as high as 19.5V during various
conditions, a zener diode with the appropriate voltage rating must be added between the GATE and OUT pins if
the maximum V
GS
rating of the selected MOSFET is less than 19.5V. The external zener diode must have a
forward current rating of at least 260 mA.
When the system voltage is initially applied, the GATE pin is held low by a 260 mA pull-down current. This helps
prevent an inadvertent turn-on of the MOSFET through its drain-gate capacitance as the applied system voltage
increases.
During the insertion time (t1 in Figure 23) the GATE pin is held low by a 2 mA pull-down current. This maintains
Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO.
Following the insertion time, during t2 in Figure 23, the gate voltage of Q1 is modulated to keep the current or
power dissipation level from exceeding the programmed levels. While in the current or power limiting mode the
TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 1.72V the
TIMER pin capacitor then discharges, and the circuit enters normal operation.
If the in-rush limiting condition persists such that the TIMER pin reached 1.72V during t2, the GATE pin is then
pulled low by the 2 mA pull-down current. The GATE pin is then held low until either a power up sequence is
initiated (LM25061-1), or until the end of the restart sequence (LM25061-2). See the Fault Timer & Restart
section.
If the system input voltage falls below the UVLO threshold, the GATE pin is pulled low by the 2 mA pull-down
current to switch off Q1.
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