Datasheet

I
IN-RMS
= I
OUT
D(1 - D)
V
DROOP
= 'I
OUTSTEP
x R
ESR
+
L x 'I
OUTSTEP
2
C
OUT
x (V
IN
- V
OUT
)
LM21215A
SNOSB87B –MARCH 2011–REVISED MARCH 2013 www.ti.com
The amount of output ripple that can be tolerated is application specific; however a general recommendation is to
keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes
preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor
the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also
affect the output voltage droop during a load transient. The peak droop on the output voltage during a load
transient is dependent on many factors; however, an approximation of the transient droop ignoring loop
bandwidth can be obtained using the following equation:
where
• C
OUT
(F) is the minimum required output capacitance
• L (H) is the value of the inductor
• V
DROOP
(V) is the output voltage drop ignoring loop bandwidth considerations
• ΔI
OUTSTEP
(A) is the load step change
• R
ESR
(Ω) is the output capacitor ESR
• V
IN
(V) is the input voltage
• V
OUT
(V) is the set regulator output voltage (7)
Both the tolerance and voltage coefficient of the capacitor should be examined when designing for a specific
output ripple or transient droop target.
INPUT CAPACITOR SELECTION
Quality input capacitors are necessary to limit the ripple voltage at the PVIN pin while supplying most of the
switch current during the on-time. Additionally, they help minimize input voltage droop in an output current
transient condition. In general, it is recommended to use a ceramic capacitor for the input as it provides both a
low impedance and small footprint. Use of a high grade dielectric for the ceramic capacitor, such as X5R or X7R,
will provide improved performance over temperature and also minimize the DC voltage derating that occurs with
Y5V capacitors. The input capacitors should be placed as close as possible to the PVIN and PGND pins.
Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good
approximation for the required ripple current rating is given by the relationship:
(8)
As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty
cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output
current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance
capacitors to provide the best input filtering for the device.
When operating at low input voltages (3.3V or lower), additional capacitance may be necessary to protect from
triggering an under-voltage condition on an output current transient. This will depend on the impedance between
the input voltage supply and the LM21215A-1, as well as the magnitude and slew rate of the output transient.
The AVIN pin requires a 1 µF ceramic capacitor to AGND and a 1Ω resistor to PVIN. This RC network will filter
inherent noise on PVIN from the sensitive analog circuitry connected to AVIN.
CONTROL LOOP COMPENSATION
The LM21215A-1 incorporates a high bandwidth amplifier between the FB and COMP pins to allow the user to
design a compensation network that matches the application. This section will walk through the various steps in
obtaining the open loop transfer function.
There are three main blocks of a voltage mode buck switcher that the power supply designer must consider
when designing the control system; the power train, modulator, and the compensated error amplifier. A closed
loop diagram is shown in Figure 33.
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